Search for dissertations about: "trivial instruction"

Found 3 swedish dissertations containing the words trivial instruction.

  2. 1. Techniques to Cancel Execution Early to Improve Processor Efficiency

    Author : Mafijul Islam; Chalmers tekniska högskola; []
    Keywords : NATURVETENSKAP; NATURAL SCIENCES; processor design; energy-efficiency; narrow-width cache; instruction reuse; zero-value cache; resource-efficient; narrow-width load; complexity-effective; small value locality; register file cache; frequent value locality; trivial instruction; silent load; high-performance; zero load;

    Abstract : The evolution of computer systems to continuously improve execution efficiency has traditionally embraced various approaches across microprocessor generations. Unfortunately, contemporary processors still suffer from several inefficiencies although they offer an unprecedented level of computing capabilities. READ MORE

  4. 2. Integrated Optimal Code Generation for Digital Signal Processors

    Author : Andrzej Bednarski; Christoph Kessler; Alain Darte; Linköpings universitet; []
    Keywords : NATURVETENSKAP; NATURAL SCIENCES; Instruction-level parallelism; integrated code generation; dynamic programming; instruction scheduling; instruction selection; clustered VLIW architecture; integer linear programming; architecture description language; Computer science; Datavetenskap;

    Abstract : In this thesis we address the problem of optimal code generation for irregular architectures such as Digital Signal Processors (DSPs).Code generation consists mainly of three interrelated optimization tasks: instruction selection (with resource allocation), instruction scheduling and register allocation. READ MORE

  5. 3. A dynamic programming approach to optimal retargetable code generation for irregular architectures

    Author : Andrzej Bednarski; Linköpings universitet; []
    Keywords : NATURVETENSKAP; NATURAL SCIENCES; Computer science; Datavetenskap;

    Abstract : In this thesis we address the problem of optimal code generation for irregular architectures such as Digital Signal Processors (DSPs). Code generation consists mainly of three tasks: instruction selection, instruction scheduling and register allocation. READ MORE