Accurate Leakage-Conscious Architecture-Level Power Estimation for SRAM-based Memory Structures

Abstract: Following Moore’s Law, technology scaling will continue providing integration capacity of billions of transistors for IC industry. As transistors keep shrinking in size, leakage power dissipation dramatically increases and gradually becomes a first-class design constraint. To provide higher performance at lower power and energy for micro-architectures, on-chip caches are growing in size and thus become a major contributor to the total leakage power dissipation in next-generation processors. In these circumstances, accurate leakage power estimation obviously is needed to allow designers to strike a balance between dynamic power and leakage power, and between total power and delay in on-chip caches. This dissertation presents a modular, hybrid power modeling methodology capable of capturing accurately both dynamic and leakage power mechanisms for on-chip caches and for SRAM arrays. The methodology successfully combines the most valuable advantage of circuit-level power estimation – high accuracy – with the flexibility of higher-level power estimation while allowing for short component characterization and estimation time. The methodology offers high-level parameterizable, but still accurate power dissipation estimation models that consist of analytical equations for dynamic power and pre-characterized leakage power values stored in tables. In addition, a modeling methodology to capture the dependence of leakage power on temperature variation, on supply-voltage scaling, and on the selection of process corners has also been presented. This methodology provides an essential extension to the proposed power models.