Antimonide Heterostructure Nanowires - Growth, Physics and Devices

Abstract: Abstract in Undetermined This thesis investigates the growth and application of antimonide heterostructure nanowires for low-power electronics. In the first part of the thesis, GaSb, InSb and InAsSb nanowire growth is presented, and the distinguishing features of the growth are described. It is found that the presence of Sb results in more than 50 at. % group-III concentration in the Au seed particle on top of the nanowires. It is further concluded that the effective V/III ratio inside the seed particle is reduced compared to the outside. This enables the suppression of radial growth with remaining high axial growth rate. Furthermore, the low effective V/III ratio may affect the crystal structure formation, which is pure Zinc-blende in all investigated Sb-based nanowires. The strong segregating properties of Sb results in a strong Sb memory effect, and a difficulty to nucleate Sb-based nanowires directly on substrates. The second part of the thesis deals with the growth and application of GaSb/InAs(Sb) nanowires for tunnel device applications. The GaSb/InAs(Sb) nanowire heterojunction has a defect-free crystal structure with an extremely abrupt heterojunction due to an inherent delay before the initiation of InAs(Sb) growth. The Sb carry-over from the GaSb growth step into the InAs growth leads to a high Sb background in the InAs(Sb) segment. The diameter of the heterojunction can be reduced below 30 nm by an in-situ annealing treatment, in which material is selectively etched from the region near the heterojunction. The performance of GaSb/InAs(Sb) tunnel diodes is modeled and measured on fabricated single nanowire devices. The diodes exhibit peak current levels of 67 kA/cm^{2} , peak-to-valley current ratio between 2 and 3 at room temperature and a tunnel current at V_{D} = -0.5 V of 1.7 MA/cm^{2} . The expected performance of GaSb/InAs(Sb) tunnel field-effect transistors is discussed and preliminary measurement data on top-gated devices with 300 nm gate length is also presented.