Growth, Physics, and Device Applications of InAs-based Nanowires

Abstract: This thesis is based on three different projects: 1) the epitaxial growth of nanowires using chemical beam epitaxy, 2) the study of electron transport through quantum dots and multiple quantum dots in nanowires at low temperature, and 3) the development of wrap gated nanowire field effect transistors. In the first part, a method of studying the diffusion of the source material on the substrate surface was developed. Nanowires were positioned in a triangular pattern on the substrate and, depending on the density of the nanowires in the arrays, the growth rate changes due to competition for available source material on the surface. A model was developed that could be fitted to experimental data using the diffusion length as one of the fitting parameters. The growth rate dependence on nanowire diameter was also studied and was satisfactorily explained by a model that takes both substrate diffusion and the Gibbs–Thomson effect into account. Nanowire heterostructures in the InAs/InP system were studied and the importance of seed particle alloying was demonstrated. The nanowires were grown from Au seed particles which alloy with indium, forming a Au–In seed particle. The composition of the particle is different during InAs and InP growth, and for each heterostructure interface the seed particle composition has to change. This affects the initial growth of InAs and InP segments. By growing two thin segments of InP in an InAs nanowire, a quantum dot was formed between the InP tunnel barriers. At low temperature (4.2 K), the electron transport through these quantum dots is governed by Coulomb interactions. In a thin quantum dot, the energy levels are raised up in energy, which allows transport through the lowest level. This transport was investigated by scanning gate microscopy to map out the electrostatic environment of the quantum dot. Furthermore, double quantum dots were studied, where the characteristics of two single quantum dots were combined to form a more complex transport system. The final part of the thesis is devoted to the development of vertical nanowire transistors with a gate that wraps around the nanowire channel. This allows enhanced control of the potential in the channel compared to conventional planar devices. Three different devices were studied: 1) an InAs device with a ~1 µm gate length, 2) an InAs device with 50 nm gate length, and 3) a heterostructure device with an InAsP segment in the channel. The InAs devices showed good current saturation and subthreshold characteristics for drive voltages around 0.5 V. The InAsP device showed a reduced off current and lower inverse subthreshold slope in comparison to similarly processed InAs reference devices.