Low Power Techniques for Fast CMOS Buffer Memories

Abstract: The thesis deals with circuit-level aspects of CMOS buffer SRAMs where the data throughput rate is a more important metric than access time or storage capacity. One aspect is the increased write cycle related power consumption that is the consequence of a high write ratio combined with a long word-length. That is addressed through the invention of a new bit-line operation mode which allows lower average bit-line voltage swing. An analysis of that operation mode in comparison to a conventional SRAM is also included in the thesis. Another aspect is the possibility to pipeline the memory access to gain lower cycle time than access time. A pipeline structure that is synchrounous (i.e., not wave-pipelined) and yet feasible in terms of clock load and power consumption is proposed and investigated through both simulations and measurements on fabricated prototypes. The research leading to this thesis has been part of a joint academic and industrial project, aiming at developing a single-chip 8 x 8 ATM switch for 10 Gbit/s links. Several experimental chips have been fabricated, verifying both components of said ATM-switch and more general buffer SRAMs. These include a 64 kbit (256 words by 256 bits) one-ported SRAM in a standard 0.8 um CMOS process, verified at 275 MHz, and a 54 kbit (256 words by 216 bits) pseudo dual-ported SRAM in the same process. Another type of buffer memories used in the ATM-switch are two-dimensional SRAM structures for combined multiplexing/parallellization as well as combined demulti-plexing/serialization of ATM-cells. These structures employ similar buffer memory techniques, including bit-line circuits experimentally verified at more than 500 MHz, also in the same 0.8 um process.