Performance of Digital Floating-Gate Circuits Operating at Subthreshold Power Supply Voltages

Abstract: All who is involved in electronic design knows that one of the critical issuesin today’s electronic is the power consumption. Designers are always looking fornew approaches in order to reduce currents while still retain performance.Floating-gate (FGMOS) circuits have previously been shown to be a promisingtechnique to improve speed and still keep the power consumption low whenpower supply is reduced below subthreshold voltage for the transistors.In this thesis, the goal is to determine how good floating-gate circuits can becompared to conventional static CMOS when the circuits are working insubthreshold. The most interesting performance parameters are speed and powerconsumption and specifically the Energy-Delay Product (EDP) that is acombination of those two. To get a view over how the performance varies and howgood the FGMOS circuits are at their best case, the circuits have been designed andsimulated for best case performance.The investigation also includes trade-offs with speed and powerconsumption for better performance, how to select floating-gate capacitances, howa large circuit fan-in will affect performance and also the influence of differentkinds of refresh circuits.The first simulations of the FGMOS circuits in a 0.13 ?m process haveseveral interesting results. First of all, in the best case it is shown that FGMOS haspotential to achieve up to 260 times in better EDP-performance compared to CMOSat 150 mV power supply. Continuing with simulations of FGMOS capacitancesshows that minimum floating-gate capacitance can be as small as 400 fF and morerealistic performance shows that EDP is 37 times better for FGMOS (with parasiticcapacitances included). Other aspects of FGMOS design have been to look at howrefresh circuits will affect performance (semi-floating-gate circuits) and how alarger fan-in will change noise margin and EDP. It turns out that refresh circuitswith the same transistor size does not give a noticeable change in performancewhile an increase of 8 times in size will give between 5 and 10 times wors EDP.When it comes to fan-in the simulations shows that a maximum fan-in of 5 ispossible at 250 mV supply and it decrease to 3 when supply voltage is reduced to150 mV.Finally, it should be kept in mind that tuning the performance of FGMOScircuits with trade-offs and by changing the floating-gate voltages to achieveresults like the ones stated above will also always affect the noise margins, NM, ofthe circuits. As a consequence of this, the NM will sometimes be so close to 1 that afabricated circuit with that NM may not be as functional as simulations suggests.The probability to design functional FGMOS circuits in subthreshold does notseem to be a problem though.