Modelling of Terahertz Planar Schottky Diodes

Abstract: This thesis deals with the modelling of THz planar Schottky diodes, focusing on analyses of the geometry- dependent parasitics and the diode chip thermal management. Moving towards higher operating frequencies, the electromagnetic couplings pose significant limitations on the diode performance. In this work, a model of the loss at high frequencies for planar diodes is developed, specifically the ohmic losses in the cathode buffer mesa is analysed. As a result, the eddy current, skin and proximity effects have been identified as important loss mechanisms in the buffer mesa. This provides an explanation to the strong frequency dependency of the series resistance, which is not explainable using conventional diode series resistance models. Due to the current crowding effect, the upper boundary of the buffer-layer thickness is approximately one skin depth at the operating frequency, whereas the lower boundary is limited by the spreading resistance at DC. In addition to the ohmic loss, the parasitic capacitance and inductance inherently limit the power coupling to the diode junction. A model is developed to analyse this limitation, i.e by studying the diode resonance requencies as a function of diode geometry. Analysis of the diode resonance frequencies as a function of the pad-to-pad distance is presented. Result shows that there is a trade-off between the parasitic capacitance and inductance, in optimising the power coupling to the junction. Based on the chip layout of frequency doublers developed by Jet Propulsion Laboratory (JPL), a systematic thermal analysis of the multiplier chip is performed. Taking the temperature-dependent material thermal properties into consideration, the result shows that the thermal resistance of the 200 GHz multiplier chip is in the order of 10^3 K/W. Meanwhile, the thermal time constant is more than tens of milliseconds. The simulation result is verified through thermal imaging using infrared microscope. Taking the thermal analysis a step further, a self-consistent electro-thermal model for the multiplier chip is proposed. The thermal model is developed using a thermal resistance matrix approach, with a linear-temperature dependency approximation of the thermal resistance. Compared to the circuit analysis without thermal model, analysis with the electro-thermal model shows a better agreement with the measured result, i.e. within 5% of the measured conversion efficiency.