Superconducting High Speed Passive Interconnects

Abstract: Superconducting digital RSFQ technology offers unique digital processing solutions for the telecommunication that allows more than three times increasing capacity of the 3G networks, makes telecommunication receivers reconfigurable and adjustable for different services, and significantly enhances security level of the data transfer over the fibers. Key features of RSFQ technology are high speed, low power and high integration density. In the current international semiconductor roadmap, RSFQ technology is listed as the least risky emerging digital technology. Over two years, the integration density of the RSFQ circuits has been increased more than twice reaching the limit of 12000 active elements per chip. The highest demonstrated clock frequency for large circuits is 60~GHz. The conventional benchmark of a static digital divider is on the limit of 360~GHz frequency. RSFQ design allows full use of commercial CAD tools and supports normal design flows with digital time/delay optimization and complete verification. RSFQ technology also gains a lot from Multi-Chip-Module (MCM) packaging. The lossless superconducting passive interconnects allow implementation of a high speed System-in-Chip (SiP). Record figures with up to 100~Gbit/s transmission for chip-to-chip communication have recently been demonstrated in the USA and Japan. The goal of the research presented in this thesis is to simulate, optimize and design of the superconducting passive interconnects for high integration density RSFQ circuits and superconducting MCM SiP. The novelty of the results is in accurate simulation of the impedance discontinuities that allowed to reduce coupling and return losses for bandwidth of 300~GHz below -20~dB limit and derivation of the general relation between passive interconnects design and fabrication process parameters. The thesis covers all required topics: models of the superconductors for electromagnetic frequency domain simulations, extraction of the equivalent circuits for time-domain simulations, optimization of the general passive structures for on-chip and inter-chip MCM high speed data links, design of the drivers and receivers for matching with active circuits, design of the high voltage driver for communication with room temperature electronics and high speed experimental verification.