On electronics for measurement systems

Abstract: This thesis collects the work performed by the author on electronics for measurement systems. The first part is the work performed on the EISCAT 3D ionospheric research radar, including two papers on the investigations on required performance, electronics design, and proof of concept signal processing. The thesis also contains work on a calibration system for mitigating signal path variations in large antenna arrays with distributed front-end electronics, enabling accurate beamforming of the received signal. Although the proposed system could in theory be entirely free from systematic errors, very large receiver dynamic range would be required in systems with many channels. Thus, in this work the measurement accuracy degradation arising when trying to reduce the dynamic range requirements has been investigated. A second part is on electronics for ultrasonic measurement systems. As one part of this part of the work, the systematic errors that arise in ultrasonic transit-time flow-meters when not utilizing the reciprocity of the flow-meter have been investigated experimentally. Based on this an integrated circuit for driving ultrasonic transducers using an arbitrary excitation waveform while maintaining constant interface impedance was designed and evaluated. By driving the ultrasonic transducer directly from a DAC the clock to output delay uncertainty was minimized. This, combined with matched on-chip receiver isolation switches enable on-line calibration against an on-chip reference DAC. These two and a work on a low-noise CMOS amplifier for ultrasonic applications are covered in three papers attached to this thesis. The third and final part is on evaluation of charge coupled devices, presented in the last paper of the thesis. It proposes a method for separating measured charge transfer inefficiency of a CCD into incomplete transfer of free charge and charge trapping in the substrate. We derive a generic model for the combined effects of charge trapping and incomplete transfer. This model further allows thecharge transfer defects of a single gate to be calculated from the combined transfer inefficiency of a larger CCD. As proof of concept the method is applied to measurement data from a CCD manufactured using a 0.18 μm PINNED photo diode CMOS process.