Search for dissertations about: "Cache"

Showing result 11 - 15 of 128 swedish dissertations containing the word Cache.

  2. 11. Securing concurrent programs with dynamic information-flow control

    Author : Pablo Buiras; Chalmers tekniska högskola; []
    Keywords : NATURVETENSKAP; NATURAL SCIENCES; dynamic; lazy evaluation; LIO; Haskell; information-flow control; cache; covert channels; covert timing channels; concurrency;

    Abstract : The work presented in this thesis focusses on dealing with timingcovert channels in dynamic information-flow control systems,particularly for the LIO library in Haskell.Timing channels are dangerous in the presence ofconcurrency. READ MORE

  4. 12. Techniques to Cancel Execution Early to Improve Processor Efficiency

    Author : Mafijul Islam; Chalmers tekniska högskola; []
    Keywords : NATURVETENSKAP; NATURAL SCIENCES; processor design; energy-efficiency; narrow-width cache; instruction reuse; zero-value cache; resource-efficient; narrow-width load; complexity-effective; small value locality; register file cache; frequent value locality; trivial instruction; silent load; high-performance; zero load;

    Abstract : The evolution of computer systems to continuously improve execution efficiency has traditionally embraced various approaches across microprocessor generations. Unfortunately, contemporary processors still suffer from several inefficiencies although they offer an unprecedented level of computing capabilities. READ MORE

  5. 13. Towards Accurate and Resource-Efficient Cache Coherence Prediction

    Author : Jim Nilsson; Chalmers tekniska högskola; []
    Keywords : NATURVETENSKAP; NATURAL SCIENCES; cache coherence protocols; performance evaluation; computer architecture; memory systems; shared memory multiprocessors;

    Abstract : The increasing speed gap between processor microarchitectures and memory technologies can potentially slow down the historical performance growth of computer systems. Parallel applicationns on shared memory multiprocessors that experience cache misses due to communication are extra susceptible to this speed difference. READ MORE

  6. 14. Compiler-Based Approaches to Reduce Memory. Access Penalties in Cache Coherent Multiprocessors

    Author : Jonas Skeppstedt; Chalmers tekniska högskola; []
    Keywords : NATURVETENSKAP; NATURAL SCIENCES; compiler analysis; hardware support; performance evaluation; memory access penalty; cache coherent multiprocessors;

    Abstract : To reduce the average time needed to perform a read or a write access in a multiprocessor, a cache is associated with each processor. A hardware mechanism is used to ensure that the replicated cache copies are consistent. This mechanism employs a protocol which controls when a node may read and/or write a shared data item. READ MORE

  7. 15. Realizing Low-Latency Internet Services via Low-Level Optimization of NFV Service Chains : Every nanosecond counts!

    Author : Alireza Farshin; Dejan Kostic; Gerald Q. Maguire Jr.; Babak Falsafi; KTH; []
    Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Low-latency Internet services; Network Function Virtualization; Low-level Optimization; Superoptimization; Last Level Cache; Internettjänster med låg fördröjning; Virtualisering av nätverksfunktioner; Optimering på låg nivå; Superoptimering; Sista-nivåns cache; Informations- och kommunikationsteknik; Information and Communication Technology;

    Abstract : By virtue of the recent technological developments in cloud computing, more applications are deployed in a cloud. Among these modern cloud-based applications, some require bounded and predictable low-latency responses. READ MORE