Search for dissertations about: "Christoph Kessler"
Showing result 6 - 10 of 16 swedish dissertations containing the words Christoph Kessler.
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6. Integrated Code Generation
Abstract : Code generation in a compiler is commonly divided into several phases: instruction selection, scheduling, register allocation, spill code generation, and, in the case of clustered architectures, cluster assignment. These phases are interdependent; for instance, a decision in the instruction selection phase affects how an operation can be scheduled. READ MORE
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7. Integrated Software Pipelining
Abstract : In this thesis we address the problem of integrated software pipelining for clustered VLIW architectures. The phases that are integrated and solved as one combined problem are: cluster assignment, instruction selection, scheduling, register allocation and spilling. READ MORE
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8. Designing a Modern Skeleton Programming Framework for Parallel and Heterogeneous Systems
Abstract : Today's society is increasingly software-driven and dependent on powerful computer technology. Therefore it is important that advancements in the low-level processor hardware are made available for exploitation by a growing number of programmers of differing skill level. READ MORE
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9. Pattern-based Programming Abstractions for Heterogeneous Parallel Computing
Abstract : Contemporary computer architectures utilize wide multi-core processors, accelerators such as GPUs, and clustering of individual computers into complex large-scale systems. These hardware trends are prevalent across computers of all sizes, from the largest supercomputers down to the smallest mobile phones. READ MORE
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10. Code Generation and Global Optimization Techniques for a Reconfigurable PRAM-NUMA Multicore Architecture
Abstract : In this thesis we describe techniques for code generation and global optimization for a PRAM-NUMA multicore architecture. We specifically focus on the REPLICA architecture which is a family massively multithreaded very long instruction word (VLIW) chip multiprocessors with chained functional units that has a reconfigurable emulated shared on-chip memory. READ MORE