Search for dissertations about: "DESIGN OF SYSTEM ON A CHIP"

Showing result 1 - 5 of 205 swedish dissertations containing the words DESIGN OF SYSTEM ON A CHIP.

2. 1. Silicon nanowire based devices for More than Moore Applications

   Author : Ganesh Jayakumar; Per-Erik Hellström; Mikael Östling; Luca Selmi; KTH; []
   Keywords : silicon nanowire; biosensor; CMOS; sequential integration; lab-on-chip; LOC; high-K; high-K integration on SiNW biosensor; ALD; fluid gate; back gate; SiNW; SiNW pixel matrix; FEOL; pattern transfer lithography; sidewall transfer lithography; STL; multi-target bio detection; BEOL; nanonets; silicon nanonets; SiNN-FET; SiNW-FET; CMOS integration of nanowires; CMOS integration of nanonets; monolithic 3D integration of nanowires; above-IC integration of nanowires; DNA detection using SiNW; SiNW biosensor; dry environment DNA detection; DNA hybridization detection using SiNW; SiNW functionalization; SiNW silanization; SiNW grafting; FEOL integration of SiNW; BEOL integration of SiNW; sequential multiplexed biodetection; biodetection efficiency of SiNW; front end of line integration of SiNW; back end of line integration of SiNW; SiNW dry environment functionalization; APTES cross-linker; accessing SiNW test site; fluorescence microscopy of SiNW; geometry of SiNW; SiNW biosensor variability; top-down fabrication of SiNW; bottom-up fabrication of SiNW; VLS method; ams foundry CMOS process; adding functionality in BEOL process; sensor integration in BEOL process; hafnium oxide; HfO2; aluminium oxide; Al2O3; TiN backgate; Nickel source drain; ISFET; ion sensitive field effect transistor; Overcoming Nernst limit of detection using SiNW; SiNW sub-threshold region operation; ASIC; SOC; SiGe selective epitaxy; epitaxial growth of SiNW; epitaxial growth of nanowires; epitaxial growth of nanonets; nickel silicide contacts; salicide process; high yield SiNW fabrication; high volume SiNW fabrication; silicon ribbon; SiRi pixel; SiRi biosensor; SiRi DNA detection; monolithic 3D integration of nanonets; above-IC integration of nanonets; impact of back gate voltage on silicon nanowire; impact of back gate voltage on SiNW; FDSOI; fully depleted silicon on insulator technology; metal backgate; wafer scale integration of SiNW; wafer scale integration of nanonets; impact of backgate voltage on CMOS inverter circuit; frequency divider; D flip-flop; Informations- och kommunikationsteknik; Information and Communication Technology;

   Abstract : Silicon nanowires (SiNW) are in the spotlight for a few years in the research community as a good candidate for biosensing applications. This is attributed to their small dimensions in nanometer scale that offers high sensitivity, label-free detection and at the same time utilizing small amount of sample. READ MORE

4. 2. High-Performance Network-on-Chip Design for Many-Core Processors

   Author : Boqian Wang; Zhonghai Lu; Kun-Chih Chen; KTH; []
   Keywords : NATURVETENSKAP; NATURAL SCIENCES; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Network-on-Chip; Chip Multi Many-core Processors; Multiprocessor System-on-Chip; High-Performance Computing; Cache Coherence; Virtual Channel Reservation; Admission Control; Artificial Neural Network; AXI4; Quality of Service; Network-on-Chip; Chip Multi Many-core Processors; Multiprocessor Sys-tem on a Chip; High-Performance Computing; Cache Coherence; Virtual Channel Reser-vation; Admission Control; Artificial Neural Network; AXI4; Quality of Servic; Informations- och kommunikationsteknik; Information and Communication Technology;

   Abstract : With the development of on-chip manufacturing technologies and the requirements of high-performance computing, the core count is growing quickly in Chip Multi/Many-core Processors (CMPs) and Multiprocessor System-on-Chip (MPSoC) to support larger scale parallel execution. Network-on-Chip (NoC) has become the de facto solution for CMPs and MPSoCs in addressing the communication challenge. READ MORE

5. 3. Design and Analysis of On-Chip Communication for Network-on-Chip Platforms

   Author : Zhonghai Lu; Axel Jantsch; Kees Goossens; KTH; []
   Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; On-Chip Communication; Network-on-Chip; System-on-Chip; Electronics; Elektronik;

   Abstract : Due to the interplay between increasing chip capacity and complex applications, System-on-Chip (SoC) development is confronted by severe challenges, such as managing deep submicron effects, scaling communication architectures and bridging the productivity gap. Network-on-Chip (NoC) has been a rapidly developed concept in recent years to tackle the crisis with focus on network-based communication. READ MORE

6. 4. Network on Chip : Performance Bound and Tightness

   Author : Xueqian Zhao; Zhonghai Lu; José Flich Cardo; KTH; []
   Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Network-on-Chip; Performance analysis; Network Calculus; Informations- och kommunikationsteknik; Information and Communication Technology;

   Abstract : Featured with good scalability, modularity and large bandwidth, Network-on-Chip (NoC) has been widely applied in manycore Chip Multiprocessor (CMP) and Multiprocessor System-on-Chip (MPSoC) architectures. The provision of guaranteed service emerges as an important NoC design problem due to the application requirements in Quality-of-Service (QoS). READ MORE

7. 5. Studies on Design Automation of Analog Circuits : the Design Flow

   Author : Emil Hjalmarson; Svensson Mattiasson; Linköpings universitet; []
   Keywords : TECHNOLOGY; TEKNIKVETENSKAP;

   Abstract : During the past few years the concept of system-on-chip (SoC) have become an important segment in the market of integrated circuits. This recent development have increased not only the number of devices and the functionality that can be put on a chip, but the chips now includes both digital and analog circuits. READ MORE