Search for dissertations about: "Erik Hagersten"
Showing result 1 - 5 of 21 swedish dissertations containing the words Erik Hagersten.
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1. Methods for run time analysis of data locality
Abstract : The growing gap between processor clock speed and DRAM access time puts new demands on software and development tools. Deep memory hierarchies and high cache miss penalties in present and emerging computer systems make execution time sensitive to data locality. READ MORE
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2. Efficient and Flexible Characterization of Data Locality through Native Execution Sampling
Abstract : Data locality is central to modern computer designs. The widening gap between processor speed and memory latency has introduced the need for a deep hierarchy of caches. Thus, the performance of an application is to a large extent dependent on the amount of data locality the caches can exploit. READ MORE
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3. Understanding Task Parallelism : Providing insight into scheduling, memory, and performance for CPUs and Graphics
Abstract : Maximizing the performance of computer systems while making them more energy efficient is vital for future developments in engineering, medicine, entertainment, etc. However, the increasing complexity of software, hardware, and their interactions makes this task difficult. READ MORE
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4. Advances Towards Data-Race-Free Cache Coherence Through Data Classification
Abstract : Providing a consistent view of the shared memory based on precise and well-defined semantics—memory consistency model—has been an enabling factor in the widespread acceptance and commercial success of shared-memory architectures. Moreover, cache coherence protocols have been employed by the hardware to remove from the programmers the burden of dealing with the memory inconsistency that emerges in the presence of the private caches. READ MORE
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5. Efficient methods for application performance analysis
Abstract : To reduce latency and increase bandwidth to memory, modern microprocessors are designed with deep memory hierarchies including several levels of caches. For such microprocessors, the service time for fetching data from off-chip memory is about two orders of magnitude longer than fetching data from the level-one cache. READ MORE