Search for dissertations about: "FABRICATION CMOS"

Showing result 1 - 5 of 47 swedish dissertations containing the words FABRICATION CMOS.

  1. 1. Silicon nanowire based devices for More than Moore Applications

    Author : Ganesh Jayakumar; Per-Erik Hellström; Mikael Östling; Luca Selmi; KTH; []
    Keywords : silicon nanowire; biosensor; CMOS; sequential integration; lab-on-chip; LOC; high-K; high-K integration on SiNW biosensor; ALD; fluid gate; back gate; SiNW; SiNW pixel matrix; FEOL; pattern transfer lithography; sidewall transfer lithography; STL; multi-target bio detection; BEOL; nanonets; silicon nanonets; SiNN-FET; SiNW-FET; CMOS integration of nanowires; CMOS integration of nanonets; monolithic 3D integration of nanowires; above-IC integration of nanowires; DNA detection using SiNW; SiNW biosensor; dry environment DNA detection; DNA hybridization detection using SiNW; SiNW functionalization; SiNW silanization; SiNW grafting; FEOL integration of SiNW; BEOL integration of SiNW; sequential multiplexed biodetection; biodetection efficiency of SiNW; front end of line integration of SiNW; back end of line integration of SiNW; SiNW dry environment functionalization; APTES cross-linker; accessing SiNW test site; fluorescence microscopy of SiNW; geometry of SiNW; SiNW biosensor variability; top-down fabrication of SiNW; bottom-up fabrication of SiNW; VLS method; ams foundry CMOS process; adding functionality in BEOL process; sensor integration in BEOL process; hafnium oxide; HfO2; aluminium oxide; Al2O3; TiN backgate; Nickel source drain; ISFET; ion sensitive field effect transistor; Overcoming Nernst limit of detection using SiNW; SiNW sub-threshold region operation; ASIC; SOC; SiGe selective epitaxy; epitaxial growth of SiNW; epitaxial growth of nanowires; epitaxial growth of nanonets; nickel silicide contacts; salicide process; high yield SiNW fabrication; high volume SiNW fabrication; silicon ribbon; SiRi pixel; SiRi biosensor; SiRi DNA detection; monolithic 3D integration of nanonets; above-IC integration of nanonets; impact of back gate voltage on silicon nanowire; impact of back gate voltage on SiNW; FDSOI; fully depleted silicon on insulator technology; metal backgate; wafer scale integration of SiNW; wafer scale integration of nanonets; impact of backgate voltage on CMOS inverter circuit; frequency divider; D flip-flop; Informations- och kommunikationsteknik; Information and Communication Technology;

    Abstract : Silicon nanowires (SiNW) are in the spotlight for a few years in the research community as a good candidate for biosensing applications. This is attributed to their small dimensions in nanometer scale that offers high sensitivity, label-free detection and at the same time utilizing small amount of sample. READ MORE

  2. 2. Micro- and Millimeter Wave CMOS Beamforming Receivers

    Author : Andreas Axholt; Institutionen för elektro- och informationsteknik; []
    Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; beamforming; CMOS; front-end; microwave; millimeter wave; phase-locked loop; phased-array;

    Abstract : The available bandwidth in wireless communication systems, such as the 802.11 family, is very limited. Together with the ever increasing data traffic, this causes problems. New possibilities are, however, available thanks to wide license-free bandwidth allocated at higher frequencies. READ MORE

  3. 3. Solid-state nanopores : fabrication and applications

    Author : Shuangshuang Zeng; Zhen Zhang; Amit Meller; Uppsala universitet; []
    Keywords : solid-state nanopore; truncated-pyramidal nanopore; nanopore array; pore size reduction; individual addressability; microfluidics; translocation.; Teknisk fysik med inriktning mot elektronik; Engineering Science with specialization in Electronics;

    Abstract : Nanopores are of great interest in study of DNA sequencing, protein profiling and power generation. Among them, solid-state nanopores show obvious advantages over their biological counterparts in terms of high chemical stability and reusability as well as compatibility with the existing CMOS fabrication techniques. READ MORE

  4. 4. Fabrication, characterization, and modeling of metallic source/drain MOSFETs

    Author : Valur Gudmundsson; Per-Erik Hellström; Yee-Chia Yeo; KTH; []
    Keywords : ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Metallic source drain; contact resistivity; Monte Carlo; NiSi; PtSi; SOI; UTB; tri-gate; FinFET; multiple-gate; nanowire; MOSFET; CMOS; Schottky barrier; silicide; SALICIDE;

    Abstract : As scaling of CMOS technology continues, the control of parasitic source/drain (S/D) resistance (RSD) is becoming increasingly challenging. In order to control RSD, metallic source/drain MOSFETs have attracted significant attention, due to their low resistivity, abrupt junction and low temperature processing (≤700 °C). READ MORE

  5. 5. Vertical Heterostructure III-V MOSFETs for CMOS, RF and Memory Applications

    Author : Adam Jönsson; Nanoelektronik; []
    Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Nanowire; MOSFET; CMOS; RRAM; III-V; InAs; GaSb; InGaAs; Heterostructure; vertical; nanowire NW ; MOSFET; III-V materials; RRAM; RF; CMOS; InAs; GaSb; InGaAs; heterostructure; Vertical nanowire;

    Abstract : This thesis focuses mainly on the co-integration of vertical nanowiren-type InAs and p-type GaSb MOSFETs on Si (Paper I & II), whereMOVPE grown vertical InAs-GaSb heterostructure nanowires areused for realizing monolithically integrated and co-processed all-III-V CMOS.Utilizing a bottom-up approach based on MOVPE grown nanowires enablesdesign flexibilities, such as in-situ doping and heterostructure formation,which serves to reduce the amount of mask steps during fabrication. READ MORE