Search for dissertations about: "Field Programmable Gate Array"

Showing result 1 - 5 of 18 swedish dissertations containing the words Field Programmable Gate Array.

  1. 1. Field Programmable Gate Arrays and Reconfigurable Computing in Automatic Control

    Author : Carl Wilhelmsson; Lunds universitet.; Lund University.; [2007]
    Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; systems analysis; FPGA; Field Programmable Gate Array; programming; Compendex: Field programmable gate arrays FPGA ; programming environments; computer science; programmable controllers; observers; adaptive control; modelling; closed loop systems; logic CAD; control systems; reconfigurable architectures; field programmable gate arrays; Computer Programming; telecommunication control; Control system applications; Real time control; Computer control systems; Control systems; Engine Control; Heat release analysis; Cylinder pressure; power-train control; Vehicle control; High speed; Rapid Prototyping; Combustion control; Automotive control; Control application; High frequency; Computer control; Feedback Control; Closed loop systems; Control; Reconfigurable computing; Reconfigurable hardware; VLSI; Closed loop control; programmable logic arrays; Automatic Control; System on Chip SoC ;

    Abstract : New combustion engine principles increase the demands on feedback combustion control, at the same time economical considerations currently enforce the usage of low-end control hardware limiting implementation possibilities. Significant development is simultaneously and continuously carried out within the field of Field Programmable Gate Arrays (FPGAs). READ MORE

  2. 2. Dynamically Reconfigurable Resource Array

    University dissertation from Stockholm : KTH Royal Institute of Technology

    Author : Muhammad Ali Shami; KTH.; [2012]
    Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; DRRA; CGRA; FPGA; VLSI; ASIC; Embedded systems; Coarse grain reconfigurable architecture; reconfigurable computing;

    Abstract : The goals set by the International Technology Roadmap for Semiconductors (ITRS) for the consumer portable category, to be realized by 2020, are 1000X improvement in performance with only 40\% increase in power budget and no increase in design team size. To meet these goals, the challenges facing the VLSI community are gaps in architecture efficacy, design productivity and battery capacity. READ MORE

  3. 3. On Hardware Implementation of Discrete-Time Cellular Neural Networks

    University dissertation from Department of Electrical and Information Technology, Lund University

    Author : Suleyman Malki; Lunds universitet.; Lund University.; [2008]
    Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Circuit switching; Network on Chip; Vein feature extraction; Velocity measurement; Discrete-Time Cellular Neural Network; Switched broadcast; Serialized broadcast; Cellular Neural Network; Field- Programmable Gate-Array; Image processing.;

    Abstract : Cellular Neural Networks are characterized by simplicity of operation. The network consists of a large number of nonlinear processing units; called cells; that are equally spread in the space. READ MORE

  4. 4. Dynamically Reconfigurable Architectures for Real-time Baseband Processing

    University dissertation from Department of Electrical and Information Technology, Lund University

    Author : Chenxin Zhang; Lunds universitet.; Lund University.; Lunds universitet.; Lund University.; [2014]
    Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Reconfigurable Computing; Coarse-Grained Architecture; Dynamic Reconfiguration; SIMD; VLIW; ASIP; Vector Processor; Baseband Processing; OFDM; MIMO; Channel Estimation; Symbol Detection.;

    Abstract : Motivated by challenges from today's fast-evolving wireless communication standards and soaring silicon design cost, it is important to design a flexible hardware platform that can be dynamically reconfigured to adapt to current operating scenarios, provide seamless handover between different communication networks, and extend the longevity of advanced systems. Moreover, increasingly sophisticated baseband processing algorithms pose stringent requirements of real-time processing for hardware implementations, especially for power-budget limited mobile terminals. READ MORE

  5. 5. System-Level Architectural Hardware Synthesis for Digital Signal Processing Sub-Systems

    University dissertation from Stockholm : KTH Royal Institute of Technology

    Author : Shuo Li; KTH.; [2015]
    Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Electrical Engineering; Elektro- och systemteknik;

    Abstract : This thesis presents a novel system-level synthesis framework called System-Level Architectural Synthesis Framework (SYLVA), which synthesizes DigitalSignal Processing (DSP) sub-systems modeled by synchronous data ?ow intohardware implementations in Application-Specific Integrated Circuit (ASIC),Field-Programmable Gate Array (FPGA) or Coarse-Grained ReconfigurableArchitecture (CGRA) style. SYLVA synthesizes in terms of pre-characterizedFunction Implementations (FIMPs). READ MORE