Search for dissertations about: "Instruction Scheduling"
Showing result 6 - 10 of 20 swedish dissertations containing the words Instruction Scheduling.
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6. Integrated Register Allocation and Instruction Scheduling with Constraint Programming
Abstract : This dissertation proposes a combinatorial model, program representations, and constraint solving techniques for integrated register allocation and instruction scheduling in compiler back-ends. In contrast to traditional compilers based on heuristics, the proposed approach generates potentially optimal code by considering all trade-offs between interdependent decisions as a single optimization problem. READ MORE
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7. Locality-aware Scheduling and Characterization of Task-based Programs
Abstract : Modern computer architectures expose an increasing number of parallel features supported by complex memory access and communication structures. Currently used task scheduling techniques perform poorly since they focus solely on balancing computation load across parallel features and remain oblivious to locality properties of support structures. READ MORE
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8. Leveraging Existing Microarchitectural Structures to Improve First-Level Caching Efficiency
Abstract : Low-latency data access is essential for performance. To achieve this, processors use fast first-level caches combined with out-of-order execution, to decrease and hide memory access latency respectively. READ MORE
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9. Exploiting Fine-grain Parallelism in Concurrent Constraint Languages
Abstract : This dissertation presents the design, implementation, and evaluation of a system that exploits fine-grain implicit parallelism in concurrent constraint programming language. The system is able to outperform a C implementation of an algorithm with complex dependencies without any user annotations. READ MORE
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10. Finding and Exploiting Memory-Level-Parallelism in Constrained Speculative Architectures
Abstract : One of the main performance bottlenecks of processors today is the discrepancy between processor and memory speed, known as the memory wall. While the processor executes instructions at a high pace, the memory is too slow to provide data in a timely manner. READ MORE