Search for dissertations about: "NoC"

Showing result 1 - 5 of 35 swedish dissertations containing the word NoC.

2. 1. Exploring trade-offs between Latency and Throughput in the Nostrum Network on Chip

   Author : Erland Nilsson; Johnny Öberg; Daniel Wiklund; KTH; []
   Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Micro electronics; Nostrum; Network on Chip; NoC; on-chip networks; micro networks; Nätverk på kisel; Nätverk på chip; Other electrical engineering; electronics and photonics; Övrig elektroteknik; elektronik och fotonik;

   Abstract : During the past years has the Nostrum Network on Chip (NoC) been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties (IP) on a single chip. READ MORE

4. 2. Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture

   Author : Awet Yemane Weldezion; Hannu Tenhunen; Lirong Zheng; Tapani Ahonen; KTH; []
   Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Alpha-model; Average distance; B-Model; NoC; Zero-load predictive model; deflection routing; q-routing;

   Abstract : Three-Dimensional (3D) integration of circuits based on die and wafer stacking using through-silicon-via is a critical technology in enabling "more-than-Moore", i.e. functional integration of devices beyond pure scaling ("more Moore"). READ MORE

5. 3. Reconfigurable NoC and Processors Tolerant to Permanent Faults

   Author : Alirad Malek; Chalmers tekniska högskola; []
   Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Networks-on-Chip; Fault Tolerance; Permanent Faults; Reconfigurable Hardware; Adaptive processors;

   Abstract : Advances in semiconductor industry have led to reduced transistor dimensions andincreased device density, but inevitably they have compromised the reliability of moderncomputing systems. In this thesis, we address the reliability problemby exploitinghardware reconfiguration for tolerating permanent faults. READ MORE

6. 4. Efficient Memory Access and Synchronization in NoC-based Many-core Processors

   Author : Xiaowen Chen; Zhonghai Lu; Umit Ogras; KTH; []
   Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Many-core; Network-on-Chip; Distributed Shared Memory; Microcode; Virtual-to-physical Address Translation; Memory Access Fairness; Barrier Synchronization; Cooperative Communication; Informations- och kommunikationsteknik; Information and Communication Technology;

   Abstract : In NoC-based many-core processors, memory subsystem and synchronization mechanism are always the two important design aspects, since mining parallelism and pursuing higher performance require not only optimized memory management but also efficient synchronization mechanism. Therefore, we are motivated to research on efficient memory access and synchronization in three topics, namely, efficient on-chip memory organization, fair shared memory access, and efficient many-core synchronization. READ MORE

7. 5. A model-based design approach for heterogeneous NoC-based MPSoCs on FPGA

   Author : Francesco Robino; Johnny Öberg; Shashi Kumar; KTH; []
   Keywords : System-level design; platform-based designembedded systems; field programmable gate arrays; integrated circuit design; integrated circuit modelling; network-on-chip; FPGA; NoC-based MPSoC; Simulink; common semantics domain; dataflow applications; design flow; embedded system; multiprocessor systems; network-on-chip; Computational modeling; Field programmable gate arrays; Mathematical model; Program processors; Prototypes; Semantics; ;

   Abstract : Network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs) are promising candidates for future multi-processor embedded platforms, which are expected to be composed of hundreds of heterogeneous processing elements (PEs) to potentially provide high performances. However, together with the performances, the systems complexity will increase, and new high level design techniques will be needed to efficiently model, simulate, debug and synthesize them. READ MORE