Search for dissertations about: "System-on-Chip"
Showing result 6 - 10 of 59 swedish dissertations containing the word System-on-Chip.
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6. Dual Data Rate Network-on-Chip Architectures
Abstract : Networks-on-Chip (NoCs) are becoming increasing important for the performance of modern multi-core systems-on-chip. The performance of current NoCs is limited, among others, by two factors: their limited clock frequency and long router pipeline. The clock frequency of a network defines the limits of its saturation throughput. READ MORE
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7. System-on-Chip test scheduling with defect-probability and temperature considerations
Abstract : Electronic systems have become highly complex, which results in a dramatic increase of both design and production cost. Recently a core-based system-on-chip (SoC) design methodology has been employed in order to reduce these costs. READ MORE
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8. Temperature Aware and Defect-Probability Driven Test Scheduling for System-on-Chip
Abstract : The high complexity of modern electronic systems has resulted in a substantial increase in the time-to-market as well as in the cost of design, production, and testing. Recently, in order to reduce the design cost, many electronic systems have employed a core-based system-on-chip (SoC) implementation technique, which integrates pre-defined and pre-verified intellectual property cores into a single silicon die. READ MORE
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9. A System-Level Framework for Energy and Performance Estimation in System-on-Chip Architectures
Abstract : Shifting the design entry point up to the system level is the most important countermeasure adopted to manage the increasing complexity of SoCs. The reason is that decisions taken at this level, early in the design cycle, have the greatest impact on the final design in terms of performance, energy efficiency and silicon area occupation. READ MORE
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10. An Integrated System-Level Design for Testability Methodology
Abstract : HARDWARE TESTING is commonly used to check whether faults exist in a digital system. Much research has been devoted to the development of advanced hardware testing techniques and methods to support design for testability (DFT). READ MORE
