Search for dissertations about: "VLSI Implementation"

Showing result 1 - 5 of 23 swedish dissertations containing the words VLSI Implementation.

  2. 1. Synchoros VLSI Design Style

    Author : Dimitrios Stathis; Ahmed Hemani; Anders Lansner; Christian Weis; Dimitrios Soudris; KTH; []
    Keywords : ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; VLSI; ASIC; CGRA; hardware architectures; synchoros VLSI; SiLago; eBrain; BCPNN; Electrical Engineering; Elektro- och systemteknik;

    Abstract : Computers have become essential to everyday life as much as electricity, communications and transport. That is evident from the amount of electricity we spend to power our computing systems. According to some reports it is estimated to be ≈ 7% of the total consumption worldwide. READ MORE

  4. 2. Baseband Processing for 5G and Beyond: Algorithms, VLSI Architectures, and Co-design

    Author : Mojtaba Mahdavi; Institutionen för elektro- och informationsteknik; []
    Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; VLSI Implementation; Hardware architectures; ASIC implementation; FPGA implementation; CMOS Technology; Baseband Processing; Massive MIMO; 5G New Radio; Beyond 5G; Co-Design; FFT processor; OFDM modulation; wireless communications; Massive MIMO Detection; Angular domain processing; Zero forcing; Systolic array; Non-linear detector; Channel Sparsity; Channel compression; Linear detector; Channel coding; Spatial coupling; Turbo-like codes; Spatially coupled serially concatenated codes; Threshold analysis; Decoder architecture; BCJR algorithm; MAP algorithm; Coupling memory; Window decoding; Complexity analysis; Performance Evaluation; Throughput; Decoding Latency; Silicon area; Design tradeoffs; Interleaver architecture; Memory requirements; Matrix multiplication; Channel state information CSI ; Cholesky decomposition; Tanner graph; Trellis codes; Convolutional encoder; Code design; Puncturing; Reordering circuit; wireless communication system; digital electronic;

    Abstract : In recent years the number of connected devices and the demand for high data-rates have been significantly increased. This enormous growth is more pronounced by the introduction of the Internet of things (IoT) in which several devices are interconnected to exchange data for various applications like smart homes and smart cities. READ MORE

  5. 3. Manufacturability in the Nanometer Era: Regularity considerations in VLSI Circuits

    Author : Kasyab Parmesh Subramaniyan; Chalmers University of Technology; []
    Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Regular Fabrics; Shifters; Barrel Shifter; ASIC; TDM; Bricks; Wired; Transistor; VLSI.; Multipliers; CMOS; HPM; Regularity; SoC; Arithmetic; Circuits;

    Abstract : Each reduction of the technology node has, along with improvements in IC fabricationtechnology, been the main driver in delivering the demand for function rich, integratedmobile electronics that are so prevalent. As devices keep growing smaller and geometriesapproach the order of a few atomic layers, it is increasingly difficult to achievecost-effective mass production for reasons related to performance and fabrication capability. READ MORE

  6. 4. Design Issues in VLSI Implementation of Image Processing Hardware Accelerators - Methodology and Implementation

    Author : Hongtu Jiang; Institutionen för elektro- och informationsteknik; []
    Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Signal processing; Bildbehandling; image processing; Imaging; Teknik; Technological sciences; Controller Synthesis; Circuit design; FPGA; Image convolution; Image processing; Video segmentation; Signalbehandling; Electronics; Elektronik;

    Abstract : With the increasing capacity in today's hardware system design enabled by technology scaling, image processing algorithms with substantially more complexity can be implemented in a single chip with real-time performance. Combined with the demand for low power consumption or larger resolution seen in many applications such as mobile devices and HDTV, new design methodologies and hardware architectures are constantly called for to bridge the gap between designers productivity and what the technology could offer. READ MORE

  7. 5. Trellis Decoding: From Algorithm to Flexible Architectures

    Author : Matthias Kamuf; Institutionen för elektro- och informationsteknik; []
    Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Electronics; Signalbehandling; Signal processing; VLSI; Viterbi algorithm; trellis decoding; TCM; survivor path; flexibility; convolutional codes; ACS; ASIC; Elektronik; Telecommunication engineering; Telekommunikationsteknik;

    Abstract : Trellis decoding is a popular method to recover encoded information corrupted during transmission over a noisy channel. Prominent members of this class of decoding algorithms are the Viterbi algorithm, which provides maximum likelihood estimates, and the BCJR algorithm, which is a maximum a posteriori estimator commonly used in iterative decoding. READ MORE