Search for dissertations about: "array architecture"

Showing result 1 - 5 of 50 swedish dissertations containing the words array architecture.

  2. 1. Code Manipulation : Architecture In-Between Universal and Specific Urban Space

    Author : Per-Johan Dahl; Institutionen för arkitektur och byggd miljö; []
    Keywords : HUMANIORA; HUMANITIES;

    Abstract : Experiences from both academia and practice demonstrate that the legal instruments that comprise the primary tool for carrying out city planning in the U.S. have grown increasingly complex and abstract. READ MORE

  4. 2. Dynamically Reconfigurable Resource Array

    Author : Muhammad Ali Shami; Ahmed Hemani; S.K Nandy; KTH; []
    Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; DRRA; CGRA; FPGA; VLSI; ASIC; Embedded systems; Coarse grain reconfigurable architecture; reconfigurable computing;

    Abstract : The goals set by the International Technology Roadmap for Semiconductors (ITRS) for the consumer portable category, to be realized by 2020, are 1000X improvement in performance with only 40\% increase in power budget and no increase in design team size. To meet these goals, the challenges facing the VLSI community are gaps in architecture efficacy, design productivity and battery capacity. READ MORE

  5. 3. Baseband Processing for 5G and Beyond: Algorithms, VLSI Architectures, and Co-design

    Author : Mojtaba Mahdavi; Institutionen för elektro- och informationsteknik; []
    Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; VLSI Implementation; Hardware architectures; ASIC implementation; FPGA implementation; CMOS Technology; Baseband Processing; Massive MIMO; 5G New Radio; Beyond 5G; Co-Design; FFT processor; OFDM modulation; wireless communications; Massive MIMO Detection; Angular domain processing; Zero forcing; Systolic array; Non-linear detector; Channel Sparsity; Channel compression; Linear detector; Channel coding; Spatial coupling; Turbo-like codes; Spatially coupled serially concatenated codes; Threshold analysis; Decoder architecture; BCJR algorithm; MAP algorithm; Coupling memory; Window decoding; Complexity analysis; Performance Evaluation; Throughput; Decoding Latency; Silicon area; Design tradeoffs; Interleaver architecture; Memory requirements; Matrix multiplication; Channel state information CSI ; Cholesky decomposition; Tanner graph; Trellis codes; Convolutional encoder; Code design; Puncturing; Reordering circuit; wireless communication system; digital electronic;

    Abstract : In recent years the number of connected devices and the demand for high data-rates have been significantly increased. This enormous growth is more pronounced by the introduction of the Internet of things (IoT) in which several devices are interconnected to exchange data for various applications like smart homes and smart cities. READ MORE

  6. 4. Three Specialized Computer Architectures for Functional Program Execution

    Author : Jonas Vasell; Chalmers tekniska högskola; []
    Keywords : NATURVETENSKAP; NATURAL SCIENCES; computer architectures; G-machine; programming languages; program compilation techniques; VLSI implementation; performance; array architecture;

    Abstract : Functional programming languages offer a new programming paradigm with many advantages over the more conventional imperative or procedural programming languages. However, these new languages are not as well adapted to the existing computers as the conventional languages, which results in low performance. READ MORE

  7. 5. Hardware Architecture for Protocol Processing

    Author : Tomas Henriksson; Axel Jantsch; Linköpings universitet; []
    Keywords : TECHNOLOGY; TEKNIKVETENSKAP;

    Abstract : Protocol processing is increasingly important. Through the years the hardware architectures for network equipment have evolved constantly. It is important to make a difference between terminals and routers and the different processing tasks they encounter. It is also important to analyze in detail the functional coverage of a hardware architecture. READ MORE