Search for dissertations about: "fully depleted silicon on insulator technology"

Showing result 1 - 5 of 7 swedish dissertations containing the words fully depleted silicon on insulator technology.

1. Silicon nanowire based devices for More than Moore Applications

Author : Ganesh Jayakumar; Per-Erik Hellström; Mikael Östling; Luca Selmi; KTH; []
Keywords : silicon nanowire; biosensor; CMOS; sequential integration; lab-on-chip; LOC; high-K; high-K integration on SiNW biosensor; ALD; fluid gate; back gate; SiNW; SiNW pixel matrix; FEOL; pattern transfer lithography; sidewall transfer lithography; STL; multi-target bio detection; BEOL; nanonets; silicon nanonets; SiNN-FET; SiNW-FET; CMOS integration of nanowires; CMOS integration of nanonets; monolithic 3D integration of nanowires; above-IC integration of nanowires; DNA detection using SiNW; SiNW biosensor; dry environment DNA detection; DNA hybridization detection using SiNW; SiNW functionalization; SiNW silanization; SiNW grafting; FEOL integration of SiNW; BEOL integration of SiNW; sequential multiplexed biodetection; biodetection efficiency of SiNW; front end of line integration of SiNW; back end of line integration of SiNW; SiNW dry environment functionalization; APTES cross-linker; accessing SiNW test site; fluorescence microscopy of SiNW; geometry of SiNW; SiNW biosensor variability; top-down fabrication of SiNW; bottom-up fabrication of SiNW; VLS method; ams foundry CMOS process; adding functionality in BEOL process; sensor integration in BEOL process; hafnium oxide; HfO2; aluminium oxide; Al2O3; TiN backgate; Nickel source drain; ISFET; ion sensitive field effect transistor; Overcoming Nernst limit of detection using SiNW; SiNW sub-threshold region operation; ASIC; SOC; SiGe selective epitaxy; epitaxial growth of SiNW; epitaxial growth of nanowires; epitaxial growth of nanonets; nickel silicide contacts; salicide process; high yield SiNW fabrication; high volume SiNW fabrication; silicon ribbon; SiRi pixel; SiRi biosensor; SiRi DNA detection; monolithic 3D integration of nanonets; above-IC integration of nanonets; impact of back gate voltage on silicon nanowire; impact of back gate voltage on SiNW; FDSOI; fully depleted silicon on insulator technology; metal backgate; wafer scale integration of SiNW; wafer scale integration of nanonets; impact of backgate voltage on CMOS inverter circuit; frequency divider; D flip-flop; Informations- och kommunikationsteknik; Information and Communication Technology;

Abstract : Silicon nanowires (SiNW) are in the spotlight for a few years in the research community as a good candidate for biosensing applications. This is attributed to their small dimensions in nanometer scale that offers high sensitivity, label-free detection and at the same time utilizing small amount of sample. READ MORE
2. Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator Technology

Author : Erik Säll; Mark Vesterbacka; Bengt E. Jonsson; Linköpings universitet; []
Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; flash analog-to-digital converter; ADC; silicon-on-insulator; SOI; top-down design; dynamic element matching; DEM; thermometer-to-binary encoder; flash ADC modeling; Electronics; Elektronik;

Abstract : High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. READ MORE
3. Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator CMOS Technology

Author : Erik Säll; Mark Vesterbacka; Bengt E. Jonsson; Linköpings universitet; []
Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; analog-to-digital converters; ADC; silicon-on-insulator; SOI; Electronics; Elektronik;

Abstract : A 130 nm partially depleted silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology is evaluated with respect to analog circuit implementation. We perform the evaluation through implementation of three flash analog-to-digital converters (ADCs). READ MORE
4. Germanium layer transfer and device fabrication for monolithic 3D integration

Author : Ahmad Abedin; Mikael Östling; Cor Claeys; KTH; []
Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; Monolithic; sequential; 3D; silicon; germanium; wafer bonding; etch back; germanium on insulator; GOI; Ge pFET; low temperature; Sipassivation; pn junction; Kisel; germanium; epitaxi; selektiv; pn-övergång; germanium påisolator; GOI; Ge PFET; bonding; monolitisk; sekventiell; tre dimensionell; 3D; lågtemperarad;

Abstract : Monolithic three-dimensional (M3D) integration, it has been proposed,can overcome the limitations of further circuits’ performance improvementand functionality expansion. The emergence of the internet of things (IoT) isdriving the semiconductor industry toward the fabrication of higher-performancecircuits with diverse functionality. READ MORE
5. Silicon device substrate and channel characteristics influenced by interface properties

Author : Mikael Johansson; Chalmers tekniska högskola; []
Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; channel; attenuation; zro2; interface; traps; semi-insulating; high-k; mos; cross-talk; hfo2;

Abstract : This thesis is divided in two parts, one dealing with the depleted Si/Si structure, which is a substrate behaving as a semi-insulating material intended for radio-frequency applications and the other concerning high-k gate dielectrics (dielectrics with high dielectric constant) as the replacement for silicon dioxide as MOS gate dielectric.High frequency applications of CMOS integrated circuits, to lower cost, achieve higher performance and richer functionality, depends partly on the possibility to decrease the substrate coupling between different parts of the circuit. READ MORE

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