Search for dissertations about: "gate leakage"

Showing result 1 - 5 of 25 swedish dissertations containing the words gate leakage.

  2. 1. Novel concepts for advanced CMOS : Materials, process and device architecture

    Author : Dongping Wu; KTH; []
    Keywords : CMOS technology; MOSFET; high-k; gate dielectric; ALD; surface pre-treatment; metal gate; poly-SiGe; strained SiGe; surface-channel; buried-channel; notched gate;

    Abstract : The continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. READ MORE

  4. 2. Static Power Reduction and Estimation in CMOS Circuits Considering Emerging Leakage Mechanisms

    Author : Mindaugas Drazdziulis; Chalmers tekniska högskola; []
    Keywords : NATURVETENSKAP; NATURAL SCIENCES; subthreshold; CMOS; wake-up time; power gating; gate leakage; VLSI;

    Abstract : Due to semiconductor technology advancements, the static power dissipation caused by leakage currents in CMOS circuits is growing at a much faster rate than dynamic power; the dominant power component. As a result, controlling and limiting static power becomes as crucial as controlling dynamic power. READ MORE

  5. 3. Silicon nanowire based devices for More than Moore Applications

    Author : Ganesh Jayakumar; Per-Erik Hellström; Mikael Östling; Luca Selmi; KTH; []
    Keywords : silicon nanowire; biosensor; CMOS; sequential integration; lab-on-chip; LOC; high-K; high-K integration on SiNW biosensor; ALD; fluid gate; back gate; SiNW; SiNW pixel matrix; FEOL; pattern transfer lithography; sidewall transfer lithography; STL; multi-target bio detection; BEOL; nanonets; silicon nanonets; SiNN-FET; SiNW-FET; CMOS integration of nanowires; CMOS integration of nanonets; monolithic 3D integration of nanowires; above-IC integration of nanowires; DNA detection using SiNW; SiNW biosensor; dry environment DNA detection; DNA hybridization detection using SiNW; SiNW functionalization; SiNW silanization; SiNW grafting; FEOL integration of SiNW; BEOL integration of SiNW; sequential multiplexed biodetection; biodetection efficiency of SiNW; front end of line integration of SiNW; back end of line integration of SiNW; SiNW dry environment functionalization; APTES cross-linker; accessing SiNW test site; fluorescence microscopy of SiNW; geometry of SiNW; SiNW biosensor variability; top-down fabrication of SiNW; bottom-up fabrication of SiNW; VLS method; ams foundry CMOS process; adding functionality in BEOL process; sensor integration in BEOL process; hafnium oxide; HfO2; aluminium oxide; Al2O3; TiN backgate; Nickel source drain; ISFET; ion sensitive field effect transistor; Overcoming Nernst limit of detection using SiNW; SiNW sub-threshold region operation; ASIC; SOC; SiGe selective epitaxy; epitaxial growth of SiNW; epitaxial growth of nanowires; epitaxial growth of nanonets; nickel silicide contacts; salicide process; high yield SiNW fabrication; high volume SiNW fabrication; silicon ribbon; SiRi pixel; SiRi biosensor; SiRi DNA detection; monolithic 3D integration of nanonets; above-IC integration of nanonets; impact of back gate voltage on silicon nanowire; impact of back gate voltage on SiNW; FDSOI; fully depleted silicon on insulator technology; metal backgate; wafer scale integration of SiNW; wafer scale integration of nanonets; impact of backgate voltage on CMOS inverter circuit; frequency divider; D flip-flop; Informations- och kommunikationsteknik; Information and Communication Technology;

    Abstract : Silicon nanowires (SiNW) are in the spotlight for a few years in the research community as a good candidate for biosensing applications. This is attributed to their small dimensions in nanometer scale that offers high sensitivity, label-free detection and at the same time utilizing small amount of sample. READ MORE

  6. 4. Sleep-Mode Circuit Techniques in the Presence of Gate Leakage

    Author : Mindaugas Drazdziulis; Chalmers tekniska högskola; []
    Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY;

    Abstract : .... READ MORE

  7. 5. Scaling of InGaAs/InAlAs and InAs/AlSb HEMTs for microwave/mm-wave applications

    Author : Malin Borg; Chalmers tekniska högskola; []
    Keywords : TEKNIK OCH TEKNOLOGIER; ENGINEERING AND TECHNOLOGY; metamorphic; InGaAs; gate length; pseudomorphic; InAs; AlSb; InP; Schottky layer; High electron mobility transistor HEMT ; drain bias;

    Abstract : The InGaAs/InAlAs high electron mobility transistor (HEMT) offers the highest maximum frequency of oscillation fmax and the lowest noise performance (NFmin) for microwave/mm-wave receivers. Similar to other device technologies, the performance of the InGaAs/InAlAs HEMT has gradually been improved by device scaling. READ MORE