Search for dissertations about: "high-k dielectric"
Showing result 1 - 5 of 22 swedish dissertations containing the words high-k dielectric.
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1. Electron states in high-k dielectric/silicon structures
Abstract : .... READ MORE
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2. Low-frequency noise in high-k gate stacks with interfacial layer engineering
Abstract : The rapid progress of complementary-metal-oxide-semiconductor (CMOS) integrated circuit technology became feasible through continuous device scaling. The implementation of high-k/metal gates had a significantcontribution to this progress during the last decade. However, there are still challenges regarding the reliability of these devices. READ MORE
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3. Integration of thulium silicate for enhanced scalability of high-k/metal gate CMOS technology
Abstract : High-k/metal gate stacks have been introduced in CMOS technology during the last decade in order to sustain continued device scaling and ever-improving circuit performance. Starting from the 45 nm technology node, the stringent requirements in terms of equivalent oxide thickness and gate current density have rendered the replacement of the conventional SiON/poly-Si stack unavoidable. READ MORE
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4. Silicon nanowire based devices for More than Moore Applications
Abstract : Silicon nanowires (SiNW) are in the spotlight for a few years in the research community as a good candidate for biosensing applications. This is attributed to their small dimensions in nanometer scale that offers high sensitivity, label-free detection and at the same time utilizing small amount of sample. READ MORE
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5. Novel concepts for advanced CMOS : Materials, process and device architecture
Abstract : The continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. READ MORE