Search for dissertations about: "instruction cache"

Showing result 1 - 5 of 18 swedish dissertations containing the words instruction cache.

  1. 1. Instruction cache memory : Issues in real-time systems

    Author : Filip Sebek; Mälardalens högskola; []
    Keywords : ;

    Abstract : .... READ MORE

  2. 2. A WCET Analysis Method for Pipelined Microprocessors with Cache Memories

    Author : Thomas Lundqvist; Chalmers University of Technology; []
    Keywords : real-time systems; data cache; infeasible paths; pipeline; instruction cache; dynamically scheduled processor; worst-case execution time; timing analysis; path analysis; timing anomaly;

    Abstract : When constructing real-time systems, safe and tight estimations of the worst case execution time (WCET) of programs are needed. To obtain tight estimations, a common approach is to do path and timing analyses. READ MORE

  3. 3. Techniques to Cancel Execution Early to Improve Processor Efficiency

    Author : Mafijul Islam; Chalmers University of Technology; []
    Keywords : NATURVETENSKAP; NATURAL SCIENCES; processor design; energy-efficiency; narrow-width cache; instruction reuse; zero-value cache; resource-efficient; narrow-width load; complexity-effective; small value locality; register file cache; frequent value locality; trivial instruction; silent load; high-performance; zero load;

    Abstract : The evolution of computer systems to continuously improve execution efficiency has traditionally embraced various approaches across microprocessor generations. Unfortunately, contemporary processors still suffer from several inefficiencies although they offer an unprecedented level of computing capabilities. READ MORE

  4. 4. Leveraging Existing Microarchitectural Structures to Improve First-Level Caching Efficiency

    Author : Ricardo Alves; David Black-Schaffer; Stefanos Kaxiras; Mattan Erez; Uppsala universitet; []
    Keywords : NATURAL SCIENCES; NATURVETENSKAP; NATURVETENSKAP; NATURAL SCIENCES; Energy Efficient Caching; Memory Architecture; Single Thread Performance; First-Level Caching; Out-of-Order Pipelines; Instruction Scheduling; Filter-Cache; Way-Prediction; Value-Prediction; Register-Sharing.;

    Abstract : Low-latency data access is essential for performance. To achieve this, processors use fast first-level caches combined with out-of-order execution, to decrease and hide memory access latency respectively. READ MORE

  5. 5. Securing concurrent programs with dynamic information-flow control

    Author : Pablo Buiras; Chalmers University of Technology; []
    Keywords : NATURVETENSKAP; NATURAL SCIENCES; dynamic; lazy evaluation; LIO; Haskell; information-flow control; cache; covert channels; covert timing channels; concurrency;

    Abstract : The work presented in this thesis focusses on dealing with timingcovert channels in dynamic information-flow control systems,particularly for the LIO library in Haskell.Timing channels are dangerous in the presence ofconcurrency. READ MORE