Simulation and timing verification of CMOS VLSI systems
Abstract: This thesis is based on new algorithms and methods for computer aided verification of digital CMOS VLSI systems. IC designs need to be verified before fabrication due the big costs associated with each iteration of detecting errors in the chip, re-design and refabrication. Because of the ever increasing complexity of IC designs there is an increasing need for better verification methods and tools.A new algorithm for switch-level simulation (LOS) has been developed. It is based on a local decision approach in contrast to previous approaches which makes global solutions for transistor groups. This object oriented design makes it suitable for uniform integration in a multi-level simulator.It is shown why switch-level simulators, in general, have problems with the pass transistor EXOR gate, and how it can be correctly simulated with the LDS simulator.It is also shown how LDS can be equipped with a mechanism to yield an estimate of averge power dissipation of the design, based on the simulated activity.It is not uncommon for IC designs to have low yield because the design itself is sensitive for variations of process parameters. A method to consider such parameter deviations for switch-level simulation and timing verification is presented. Warnings are then given for circuitry which are not sufficiently robust.The hierarchical timing verifier (HTV) has been developed. It can be used on the transistor level and higher levels, since it is not tailored to a specific abstraction level. The hierarchical approach implies a reduced verification cost since only unique cell types need to be analysed. HTV is independent of clocking strategy and do include skew effects. In addition, it considers deviations of process parameters, and includes a mechanism to detect fundamental design errors.Algorithms have been developed to recognize the circuit classes of combinational gate and C2MOS-gates at the transistor level. The result is timing specifications, including both delay values and timing constraints.A method has been developed to handle level-sensitive latches in timing verification, which long has been considered a serious problem.
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