Graphene spin circuits and spin-orbit phenomena in van der Waals heterostructures with topological insulators
Abstract: Spintronics offers an alternative approach to conventional charge-based information processing by using the electron spin for next-generation non-volatile memory and logic technologies. To realize such technologies, it is necessary to develop spin-polarized current sources, spin interconnects, charge-to-spin conversion processes, and gate-tunable spintronic functionalities. The recently emerged two-dimensional (2D) and topological materials represent a promising platform to realize such spin-based phenomena. Due to its small spin-orbit coupling (SOC), graphene was predicted to preserve electron spin coherence for a long time, making it an ideal material for spin communication. In contrast, topological insulators (TIs) have high SOC and develop a nontrivial band structure with insulating bulk but conducting spin-polarized surface states. Combining these materials in van der Waals heterostructures has been predicted to give rise to unique proximity-induced spin-orbit phenomena that may be used for electrical control of spin polarization. In this thesis, we experimentally prove that the large-area chemical vapor deposited (CVD) graphene is an excellent material choice for the realization of robust spin interconnects, which are capable of spin communication over channel lengths exceeding 34 μm. Utilizing such graphene, we realize a spin summation operation in multiterminal devices and employ it to construct a prototype spin majority logic gate operating with pure spin currents. In topological insulators, we electrically detect the spin-momentum locking and reveal how the bulk and surface conducting channels affect the charge-to-spin conversion efficiency. Finally, by combining graphene and TIs in hybrid devices, we confirm the emergence of a strong proximity-induced SOC with a Rashba spin texture in graphene. We further show that in such heterostructures a spin-charge conversion capability is induced in graphene via the spin-galvanic effect at room temperature and reveal its strong tunability in magnitude and sign by the gate voltage. These findings demonstrate the robust performance of graphene as a spin interconnect for emerging spin-logic architectures and present all-electrical and gate-tunable spintronic devices based on graphene-TI heterostructures, paving the way for next-generation spin-based computing.
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