Clocking of high speed CMOS VLSI systems
Abstract: Two consequences of high level circuit integration may be increasing cost of design and cost of interconnections. Interconnection is expensive in terms of silicon area, speed and power. As far as timing is concerned. schemes of future VLSI systems may not be a simple extension of those used in the existing LSI circuits. This is because the relative importance of clock skew increases as the MOS technology develops and interconnections become slower and slower. Clock skew makes the design of VLSI synchronous circuits ineffective, complicated and failure prone. For a synchronous scheme to be useful in the VLSI environment and enjoy the experiences gained by designers, it must develop to a fast, simple, structured and robust scheme.To alleviate the adverse effects of clock skew, technological as well as circuit techniques may be employed. We have proposed a technological solution. It is suggested that a special interconnection metal layer should be introduced into the VLSI process and used for long interconnections. It is shown that by using this technique, the interconnection delay will not be a limiting factor for the performance of synchronous systems.We have also considered circuit solutions. To this end, physical causes of clock skew are investigated. It is shown that even for optimized interconnections, traditional modes of clocking results in unacceptable time performance for high speed synchronous systems. Then a new mode of clocking is presented and analysed in detail. By using this mode of clocking, the performance of synchronous systems scales with scaling the minimum feature size of MOS transistors.We have developed a synchronous scheme that is structured, simple and general. These factors also make the CMOS systems well suited for design compilation. A circuit technique is proposed that makes the design of synchronous schemes robust. Performance of different asynchronous schemes in VLSI environment is also investigated. It is shown that synchronous schemes outperforms standard asynchronous schemes for a wide range of important applications.Finally, in order to test some of the developed rules and principles, a chip has been designed as an example. In this design, a new hardware algorithm is presented for sorting. This algorithm is based on bit-serial data processing. It is shown that this design can operate at a clock frequency determined by the computational module delays and not by the clock skew.
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