Contactless Test of Circuit Boards
Abstract: Electronics are still continuing to respond to the small-feature size requirement for economical, performance and environmental benefits. Due to the non-idealities in the manufacturing process of circuit boards, electronics production yield is never 100 %. To maintain a good reputation of a product brand, testing of circuit boards is highly recommended before shipping to the customer. Because of the strive for high density electronics, an increasing percentage of circuit boards will not be accessible for the current test approaches. New technologies as High-Density Interconnect (HDI), Through-Silicon Via (TSV), embedded chips and Sequential Build-Up (SBU) circuit boards will even further increase the challenge for the test business. Current test approaches to dense circuit boards most often require extra test pads and thus additional cost and size. Already the use of today's standard Ball Grid Array (BGA) packages has introduced difficulties to conventional Printed Circuit Boards (PCBs) testing. To deal with these challenges on testing and to enhance the current test methodologies, this thesis addresses improvements to the existing test methodologies and also proposes test approaches usable in conjunction with Sequential Build-Up (SBU) production of circuit boards. Firstly, this thesis introduces a new indirect method to test Printed Wiring Board (PWB)/PCB where probing is feasible. A Radio Frequency (RF) signal is injected into the trace under test, instead of a DC current. The phase shift between the incident and the reflected signals is measured as it carries information about the Unit Under Test (UUT). The solution implies faster and lower probing technology resources as it is possible to test against opens and shorts in one pass, it uses a single probe. Based on several cases, manufacturing defects are discriminated with significant margins. Secondly, a contactless approach for testing PCB is proposed for interconnects where probing is not feasible. A test trace is employed on another test board as a sensor, which reads the terminations of the trace of the UUT. The results have shown the feasibility of this concept to be applied to the state of the art HDI and to conventional PCBs with hidden interconnects. Design for Testability (DfT) rules have been created for robust error detection that allow fault detection in the range of a few Parts per Billion (PPB) while accounting for component specification variabilities of 10 - 20 %. It has been shown that the maximum test frequency is around 6 GHz, which is manageable.
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