Low power digital CMOS design

Abstract: This Dissertation describes research on Low Power Digital CMOS Design performed at the LSI Design Center, Department of Physics and Measurement Technology, Linkoping University, Linkoping, Sweden. The research covers Low Power CMOS Device Design, Low Power Circuit and System Technique and Power Estimations in Digital CMOS VLSI Chips.Interest in Low Power digital CMOS VLSI has increased strongly in the 90s. One reason is that the scaling of digital CMOS has led to a very large power consumption per chip. Another reason is the increased need for portable or mobile products.General low power strategies are reviewed in the first part, entitled Low Power Digital CMOS Design, of the dissertation. The review covers low power digital CMOS design from the system level, circuit level and device level point of view.In the second part of the dissertation, low power through low supply voltage has been investigated on device level, including supply voltage bounds, opportunities for power reduction without speed loss, and temperature and process induced deviations. Two main arguments against ultra low supply voltage have been discussed in this dissertation. One is the temperature induced deviation, another is the global process parameter sensitivity. The main contributions in the second part are:1. For the first time, the lower limit of Vddfor static and dynamicCMOS logic is investigated.2. For the first time, the possibility of decreasing supply voltageand maintaining high speed by threshold voltage and processoptimization is demonstrated. Two examples are 40 times and 4.8times power reduction by process optimization without speed lossfor static and dynamic logic respectively.3. The possibility of choosing process, V dd, and Vth givingtemperature independent circuit speed of digital CMOS has beendemonstrated.4. It has been demonstrated that highly reliable digital CMOSTechnology including freedom of latch-up and hot electroninduced life time reduction is achieved at low supply voltages.The three supply voltage values, one that eliminates latch-up, one that avoids hot electron induced life time reduction and one that gives temperature independent speed, are close to each other. This strongly motivates a decrease of supply voltage for digital CMOS. Combining the findings from 1 to 4, an optimized digital CMOS technology is proposed in this dissertation. It could support both static and dynamic logic, with low power, high speed, without latch-up problems, and with long life time.Before this work, there was no general description of power distribution in a digital CMOS chip. We need to know how power consumption is distributed among different parts of the chip in order to direct low power design. Therefore, in the third part of the dissertation, a method for estimation and comparison is discussed. An estimation tool has been developed and power estimation and comparison examples are given in the third part of the dissertation. Two contributions are:5. A power estimation tool has been developed. The tool has beenused to demonstrate the prospects of power savings in CMOS ]Cs.6. Power consumption has been compared for different circuitstyles, layout styles, and architectures.The estimation tool provides a general view of the power distribution in digital CMOS chips. This gives directions for further low power design research. The power consumption comparisons offer suggestions for digital low power design of highly pipelined and other kinds of systems.