Continuous-Time Delta-Sigma Modulators for Wireless Communication

Abstract: The ever increasing data rates in wireless communication require analog to digital converters (ADCs) with greater requirements on speed and accuracy, while being power efficient to prolong battery life. This dissertation contains an introduction to the field and five papers that focus on the continuous-time (CT) Delta-Sigma modulator (DSM) as ADC. Paper I analyses the performance degradation of dynamic nonlinearity in the feedback DAC of the DSM, caused by Vth mismatch in the current-switching (differential) pair of a current-steering DAC. A model is developed to study return-to-zero (RZ) and non-return-to-zero (NRZ) feedback DACs, with and without data-weighted averaging (DWA), where an RZ DAC with DWA recovers the performance. Paper II and III presents a feedback scheme for improved robustness against variations in loop delay. An RZ pulse, centered in the clock period, is used in the innermost feedback path which has the highest sensitivity to loop delay, while NRZ pulses are adopted in the outer feedback paths to reduce the sensitivity to clock jitter and lower the integrator slew rate requirements. Furthermore, the otherwise obligatory loop delay compensation path (e.g. an additional DAC and adder) could be omitted to reduce hardware complexity. A discrete-time model of the feedback scheme confirms a negligible loss in performance. The 3rd-order CT DSM in 65nm CMOS with 9MHz LTE bandwidth achieves 69/71dB SNDR/SNR and consumes 7.5mW from a 1.2V supply. Measurements with OFDM signals verify an improved tolerance to blockers outside the signal band of the DSM. Paper IV and V present two filtering ADCs, where the DSM is merged into the channel select filter to suppress the noise from the DSM. The first and second prototypes provide a 2nd- and 3rd-order channel select filtering and improve the SNDR of the DSM by 14dB and 20dB, respectively, which in theory can be exploited to reduce the DSM power consumption by four to eight times. The first prototype has a 288MHz clock frequency, a 9MHz LTE bandwidth, a 2nd-order Butterworth filter response with 12dB gain, an input-referred noise of 8.1nV/sqrt(Hz), an in/out-of-band IIP3 of 11.5/27dBVrms, and a power consumption of 11.3mW. The second prototype is clocked at 576/288MHz with an 18.5/9MHz LTE bandwidth, a Chebyshev filter response with 26dB gain, a low input-referred noise of 5nV/sqrt(Hz), and an in/out-of-band IIP3 of -8.5/20dBVrms, with a power consumption of 7.9/5.4mW for 2xLTE20/LTE20 mode. The prototype was characterized for OFDM modulated blockers and essentially meets the cellular standard LTE Rel. 11. A delay, introduced by the feedback DAC, is compensated by adjusting the filter coefficients to restore the original Chebyshev filter function. Both prototypes have state-of-the-art power efficiency compared to other filtering ADCs and are comparable or better than a stand-alone filter. Furthermore, the filtering ADC provides both filtering and A/D conversion, which suggests that the A/D conversion is included in a power efficient manner, broadly speaking "for free".