Monolithic Integrated Oscillators - Phase Noise Analysis and Inductor Modeling

Abstract: This doctoral dissertation studies voltage controlled oscillators (VCOs) that operate at low supply voltages. Due to smaller transistor sizes and lower supply voltage ratings with every new CMOS technology, voltage headroom is diminishing. Therefore, new ways to build VCOs and quadrature VCOs (QVCOs) have been sought to overcome this smaller headroom, while still maintaining the high performance of the circuits. The studies of low voltage VCOs and QVCOs in this thesis are based upon common topologies that use noisy transistors as their current sources. Transistor current sources need an extra voltage margin to operate at the expense of the oscillator's voltage swing, thereby diminishing the oscillator's performance. One elegant solution to eliminate this problem is to use an on-chip inductor as a current source. A source node inductor value is chosen such that it resonates with the stray capacitance at the second harmonic 2w0. This results in a raised impedance at this frequency, which makes the current source more ideal. Furthermore, the source node inductor has the advantage of zero voltage drop and its dynamic voltage swing can be used over the tank to increase the overall voltage headroom of the oscillator, further improving its performance. The phase noise performance of LC oscillators is set by the quality of the tank. A few years ago, on-chip inductors had low quality and were the principal factor in tank losses. Today, however, most CMOS technologies incorporate thick top metal that increase the quality of the inductors significantly. At the same time, MOS varactors operate at reduced quality because of low voltage supply, and for some bias values this quality is as low as on-chip inductors had been in the past. For this reason, modeling of monolithic inductors is here explored with a view toward co-optimizing the inductor and the limitations of low voltage operations using varactors in conjunction with the oscillator's parasitics to maximize the oscillator's performance. When the source node carries a capacitive load, both the balanced and the unbalanced states increase the phase noise contribution substantially. In the balanced state there is an increase switch time and overdrive voltages, which in turn increase the excess noise factor of the transistors. The unbalanced state also contributes phase noise because the source node capacitance opens up a path to the tank that increases with the capacitive load and frequency. The phase noise analysis of a differential LC oscillator has shown that this noise derives from both the balanced and unbalanced states during an oscillation period.