Building Blocks for Low-Voltage Analog-to-Digital Interfaces

Abstract: In today’s system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog, radio-frequency (RF), and digital integrated circuits. The rapid scaling of CMOS technology nodes presents opportunities and challenges. Benefits accrue in terms of integration density and higher switching speeds for the digital logic. However, the concomitant reduction in supply voltage and reduced gain of transistors pose obstacles to the design of highperformance analog and mixed-signal circuits such as analog front-ends (AFEs) and data converters.To achieve high DC gain, multistage amplifiers are becoming necessary in AFEs and analog-to-digital converters (ADCs) implemented in the latest CMOS process nodes. This thesis includes the design of multistage amplifiers in 40 nm and 65 nm CMOS processes. An AFE for capacitive body-coupled communication is presented with transistor schematic level results in 40 nm CMOS. The AFE consists of a cascade of amplifiers to boost the received signal followed by a Schmitt trigger which provides digital signal levels at the output. Low noise and reduced power consumption are the important performance criteria for the AFE. A two-stage, single-ended amplifier incorporating indirect compensation using split-length transistors has been designed. The compensation technique does not require the nulling resistor used in traditional Miller compensation. The AFE consisting of a cascade of three amplifiers achieves 57.6 dB DC gain with an input-referred noise power spectral density (PSD) of 4.4 nV/ while consuming 6.8 mW.Numerous compensation schemes have been proposed in the literature for multistage amplifiers. Most of these works investigate frequency compensation of amplifiers which drive large capacitive loads and require low unity-gain frequency. In this thesis, the frequency compensation schemes for high-speed, lowvoltage multistage CMOS amplifiers driving small capacitive loads have been investigated. Existing compensation schemes such as the nested Miller compensation with nulling resistor (NMCNR) and reversed nested indirect compensation (RNIC) have been applied to four-stage and three-stage amplifiers designed in 40 nm and 65 nm CMOS, respectively. The performance metrics used for comparing the different frequency compensation schemes are the unity gain  frequency, phase margin (PM), and total amount of compensation capacitance used. From transistor schematic simulation results, it is concluded that RNIC is more efficient than NMCNR.Successive approximation register (SAR) analog-to-digital converters (ADCs) are becoming increasingly popular in a wide range of applications due to their high power efficiency, design simplicity and scaling-friendly architecture. Singlechannel SAR ADCs have reached high resolutions with sampling rates exceeding 50 MS/s. Time-interleaved SAR ADCs have pushed beyond 1 GS/s with medium resolution. The generation and buffering of reference voltages is often not the focus of published works. For high-speed SAR ADCs, due to the sequential nature of the successive approximation algorithm, a high-frequency clock for the SAR logic is needed. As the digital-to-analog converter (DAC) output voltage needs to settle to the desired accuracy within half clock cycle period of the system clock, a speed limitation occurs due to imprecise DAC settling. The situation is exacerbated by parasitic inductance of bondwires and printed circuit board (PCB) traces especially when the reference voltages are supplied off-chip. In this thesis, a power efficient reference voltage buffer with small area has been implemented in 180 nm CMOS for a 10-bit 1 MS/s SAR ADC which is intended to be used in a fingerprint sensor. Since the reference voltage buffer is part of an industrial SoC, critical performance specifications such as fast settling, high power supply rejection ratio (PSRR), and low noise have to be satisfied under mismatch conditions and over the entire range of process, supply voltage and temperature (PVT) corners. A single-ended, current-mirror amplifier with cascodes has been designed to buffer the reference voltage. Performance of the buffer has been verified by exhaustive simulations on the post-layout extracted netlist.Finally, we describe the design of a 10-bit 50 MS/s SAR ADC in 65 nmCMOS with a high-speed, on-chip reference voltage buffer. In a SAR ADC, the capacitive array DAC is the most area-intensive block. Also a binary-weighted capacitor array has a large spread of capacitor values for moderate and high resolutions which leads to increased power consumption. In this work, a split binary-weighted capacitive array DAC has been used to reduce area and power consumption. The proposed ADC has bootstrapped sampling switches which meet 10-bit linearity over all PVT corners and a two-stage dynamic comparator. The important design parameters of the reference voltage buffer are derived in the context of the SAR ADC. The impact of the buffer on the ADC performance is illustrated by simulations using bondwire parasitics. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner, and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.