Digital Predistortion for the Linearization of Power Amplifiers

University dissertation from Chalmers University of Technology

Abstract: High efficiency and linearity are indispensable requirements of power amplifiers. Unfortunately they are difficult to obtain simultaneously, since high efficiency PAs are nonlinear and linear PAs may have low efficiency. In order to satisfy the efficiency and linearity requirements, designers preferred to prioritize the efficiency of PAs in the design process and to later recover the linearity using external linearization techniques or architectures. Among the linearization techniques proposed in the literature, digital predistortion (DPD) has drawn the most attention of the industrial and academic sectors because it can provide a good compromise between linearity performance and implementation complexity. This thesis investigates digital predistortion techniques to suppress nonlinear distortion in radio transmitters. The first part of this thesis provides a short introduction to the behavioral modeling of PAs, which includes a review of the most commonly known behavioral models, parameter estimation techniques, and performance evaluation criteria. The second part provides an introduction to digital predistortion linearization and reviews different parameter identification techniques for digital predistorters. A variant to the indirect learning architecture (ILA), which is the most commonly used parameter identification technique, is proposed to simplify the DPD synthesis. The concept of iterative learning control (ILC) for the linearization of PAs is introduced and a new parameter identification technique based on ILC is proposed. The third and final part of this thesis focuses on the linearization of dual-input transmitter architectures. Such architectures, which are currently attracting large research interest in the PA hardware community can offer greater efficiency and linearity than conventional PAs. The varactor-based dynamic load modulation PA architecture and dual-input Doherty PAs are discussed. A review of different linearization schemes especially designed for these kind of architectures is presented. Finally the linearization of dual-input Doherty PAs is discussed and a new linearization scheme that provides better linearity performance than existing schemes has been proposed. The improved linearity performance achieved through the techniques and methods developed in this thesis can enable a better utilization of the potential performance of existing and emerging highly efficiency PAs, and are therefore expected to have an impact in future wireless communication systems.

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