Efficient mm-Wave Transmitter Design in CMOS Technology

Abstract: An increasing demand of higher data rates in wireless communication forces the industry to look to higher frequencies to find the required bandwidths. This thesis is about analog transmitters in CMOS for millimeter-wave communication, and it focuses on improving power amplifiers and frequency generation circuits, and increase their efficiency. This thesis starts with an introduction to millimeter-wave transmitters in CMOS, standards and beamforming. It then continues with a brief introduction to millimeter-wave power amplifier design and design of local oscillators at millimeter-wave frequencies. The last part of the thesis consist of six papers, which present eleven manufactured and measured millimeter-wave circuit designs. Paper I presents a two-stage, 65-nm CMOS, Class-A PA for the 60-GHz band. It employs capacitive cross-coupling neutralization for higher differential isolation and gain, without the need to increase the power consumption. It achieves 18.5 % peak-added-efficiency. Paper II presents a varactorless VCO in 65 nm CMOS, operating in the 60-GHz band. In paper III, the efficiency of the popular source-node filtering technique for improved phase-noise performance is investigated through measurements of two same-chip 60-GHz VCOs in FD-SOI CMOS. The filtered VCO achieves a state-of-the-art figure-of-merit of -187.3 dBc/Hz. Paper IV presents two FD-SOI CMOS VCOs for the 30-GHz and the 60-GHz band, that achieve ultra-low power consumption, also at full supply voltage. In paper V, a phase-locked loop in 28-nm FD-SOI CMOS for 5G transceiver systems is proposed. Its VCO operates at around 55 GHz. The paper describes the disadvantages of using a too high input reference frequency, but also proposes a new architecture that handles the increased settling time by mode-switching. It also includes a novel charge-pump current-mismatch mitigation technique based on feedback, and a novel wideband and low-power injection-locked divide-by-three circuit. The phase-locked loop consumes only 10 mW of power, has an integrated jitter of 176 fs, and demonstrates a state-of-the-art figure-of-merit of -245 dB. Paper VI describes a wideband injection-locked divide-by-two circuit in 28-nm FD-SOI CMOS. It achieves a locking range of 30 % at the low power consumption of 4.3 mW.