Ultra-low Voltage Embedded Memories – Design Aspects and a Biomedical Use-case
Abstract: As the Internet of Things (IoT) era emerges the need for ultra-low power (ULP) devices is becoming more eminent. A research-proven approach to achieve ULP consumption is to aggressively lower the supply voltage (VDD) below or in the vicinity of the transistor threshold voltage (Vth) and operate the transistors in the subthreshold (sub-Vth) region. Operating below or near the threshold voltage, i.e., near threshold (near-Vth), incurs exponentially degrade performance, however, if tolerable, leads to a more energy efficient operation. In this doctoral thesis memory design for near-Vth and sub-Vth operation is explored using standard-cell based memories (SCMs) where the storage element, which accounts for ∼2/3 of total memory area, is replaced by a full-custom designed alternative. The designed memories are used in a biomedical circuit for atrial fibrillation detection.Paper I presents an ULP synthesizable memory using commercial standard-cells complemented with a low-leakage full-custom developed D-Latch with integrated 3-state output buffers as read-logic.Paper II presents two ULP synthesizable memories which use a full-custom developed dual-Vth D-Latch, where PMOS transistors are implemented using a lower-Vth than NMOS transistors. The read-logic is implemented using complementary metal oxide semiconductors (CMOS) multiplexers in one of the memories and a mixture of 3-state buffers and CMOS multiplexers in the second memory.Paper III presents a synthesizable memory using an area-optimized full-custom pass-latch where the pass transistors are implemented using a lower-Vth than the remaining transistors.Paper IV explores the use of a general purpose (GP) process option [instead of low power (LP)] to achieve a higher maximum frequency at ultra-low voltage (ULV) and presents a coherent summary of the different trade-offs for SCMs, i.e., area, leakage power, access speed, access energy and retention voltage.Paper V presents a wide operating range synthesizable memory designed in a 28 nm fully-depleted silicon-on-insulator (FD-SOI) process that takes advantage of the body bias capabilities to compensate for a slow corner using forward body bias (FBB).Paper VI is a case study of an atrial fibrillation (AF) detector designed for sub-Vth operation combined with an ULP memory using standard-cells. The detector is aimed to be operated together with a pacemaker on a single battery charge for 10 years.Paper VII presents energy savings by using clock- and power-gating of the AF detector presented in Paper VI.
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