Using Inhomogeneous Neuronal–Synaptic Dynamics for Spatiotemporal Pattern Recognition in Neuromorphic Processors

Abstract: Mixed-signal neuromorphic processors emulate the electrochemical dynamics of neurons and synapses using conventional CMOS transistor technology and have potential for ultra-low-power machine learning and inference. However, the energy-efficiency of such systems is dependent on sparse, time-based encoding and processing, and they are, furthermore, subject to imprecision from "device mismatch" in the inhomogeneous analog circuitry. Hence, there is a need for neurocomputational methods based on principles of dynamic neural processing for efficient use of these low-power but inhomogeneous systems.In this thesis, inspiration is drawn from a temporal feature-detection circuit in crickets for the design of excitatory–inhibitory balanced disynaptic elements, which induce neural signal-propagation delays for coincidence-based pattern recognition. Due to device mismatch, the disynaptic elements have a distribution of temporal delays when implemented in mixed-signal hardware, both between and within single neurons. Here, this is utilized as a source of the variability needed for spatiotemporal pattern representation – as a hardware-resource efficient alternative to dedicated axonal or neuronal delays or emulation of dendrites.Resulting from experiments with a DYNAP-SE neuromorphic processor connected in a closed loop with a PC and a digital oscilloscope, synaptic delays of up to 100 ms are characterized, with an intraneuronal variability of order 10 ms. Use of the synaptic delays for generating coincidence-based spatiotemporal receptive fields of up to five dimensions in single hardware neurons in a Spatiotemporal Correlator (STC) neural network is demonstrated. The energy dissipation of the balanced synaptic elements is one order of magnitude lower per lateral connection (0.65 nJ vs 9.3 nJ per spike) than the original delay-based hardware implementation of the STC network.Thus, it is shown how the inhomogeneous synaptic circuits could be utilized for resource-efficient implementation of STC network layers, in a way that enables synapse-address reprogramming as a discrete mechanism for feature tuning. The presented approach may serve as a complement to more accurate but resource-intensive delay-based coincidence detection or dendritic integration.