VLSI aspects on inversion in finite fields
Abstract: Different algorithms and architectures for inversion in finite extension fields are studied. The investigation is restricted to fields of characteristic two. Based on a simple transistor model, various architectures are compared with respect to delay, area requirement, and energy consumption.Both polynomial and normal basis representations are considered. A special investigation is made on representations of fields as tower fields. New architectures are presented and compared with previously known architectures. For tower fields, a thorough investigation is made for the case where the extension degree is a power of two. In that case the investigation is based on a classification of all possible bases of the field over its largest subfield.It is noted that normal bases, generated by irreducible all-one polynomials, are closely related to the polynomial bases which are generated by the same polynomials. Based on this observation, it is shown how architectures considered for polynomial basis representation can be modified for use with corresponding normal bases.A list of minimum weight irreducible polynomials over F2 is also given.
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