Studies on CMOS Digital-to-Analog Converters

Abstract: In this thesis we present an overview and study on digital-to-analog converters (DAC), mainly for communications applications. Especially, we look at some digital subscriber line (DSL) specifications and communication over twisted-pair channels. It is pointed out that the required resolution on the DACs in such systems is in the order of 12 to 14 bits of re solution. At the same time the bandwidth stretches from below MHz to several tens of MHz. These figures are the guiding specification throughout the thesis.In this work we consider many of converter architectures and chips. The current-steering DAC is pointed out as a suitable converter for both high speed and high resolution. We also investigate the oversampling DAC (OSDAC) and discuss its properties in detail.The performance of the converters is limited by both static and dynamic errors. The static errors are usually caused by mismatch of the components and limit the accuracy at low speed. The static performance is often described by measures of differential and integral nonlinearities, (DNL and 1NL). For communication applications these measures are not especially used for characterization of the DACs. Instead, the dynamic errors, such as settling errors, glitches, etc., are more important since they increase with higher sample rates and signal frequencies. To analyze the effect of errors it is usually easier to consider the DAC's behavior i~ frequency domain using measures, such as the spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SFDR). These  measures are normally derived from the output spectrum when a sinusoidal input signal is used. In some applications it may be necessary to use several sinusoidal tones to get relevant measures. Two common measures are the multi-tone power ratio (MTPR) and the peak-to-average ratio (PAR). The PAR of the input signal affects the maximum signal-to-noise ratio (SNR) of the converter and a small PAR is preferred since it maximizes the SNR.To help us understand how to design a converter several models and algorithmic expressions are presented. The models are verified through simulations and partially through measurements and experiments. Some of the most dominating error sources in converters, such as limited output impedance, device mismatch, and noise, are highlighted. We give suggestions on how to reduce and minimize the influence of these types of error sources. These techniques involve calibration and randomization, as well as cancellation through for example pre-distortion algorithms. We also present the basics of dynamic element matching techniques (DE M).The usage of the models is to reduce the design time and get a good understanding for fundamentallimitations on performence. Instead of time-consuming circuit-level simulations, we point out the behavioral-level and algorithmic-level simulation of the converters. Most of the models have been described in languages, such as Matlab and  Mathematica.Several chips have been implementated in CMOS and some improvement in performance has been measured from generation to generation. By comparing two similar DACs with small variations, we show how the performance of the converter depends on typical mismatches in the layout. The measurement results are analyzed by using simulation results from the proposed DAC models. By identifying distortion terms we can partially determine matching errors, output impedance, and parasitic impedance.Often the design of DACs is focused on the actual converter alone. We emphasize the need for a broad view, where a more integrated digital/analog design is considered. The typical mixed-signal and analog circuits, e.g., DAC, ADC, filters, amplifiers. In e.g. a transceiver must be co-optimized. Analog circuits mix with digital circuits and signal processing  algorithms on the same chip and we have to carefully investigate how the different subcircuits interact.We discuss the design and implementation of current-steering DACs for wideband applications. Different architectures are outlined and we emphasize the segmented DAC as the most suitable converter structure for high speed and high resolution. Here, a key design issue is to find the proper number of bits to encode into a thermometer code. This increases the digital contents of the DAC, but reduces the glitches.Further, we discuss issues involving design ofOSDACs. We use the sigma-delta modulators to reduce the number of bits representing the digital signal and then we use small and simple analog circuits, which can be optimized with respect to the device. As a design case, we select an OSDAC for ADSL applications. It is found that the requirements on the OSDAC are tough. It is emphasized that the design of an oversampling converter essentially is a filter design problem. There is a large number of possible trade-offs that can be made between the different building blocks in the OSDAC. Here, the key design issue is to define a proper cost function that lets us find a good overall solution.The thesis also presents some special converter architectures. A DAC's behavior for different input codes is examined. The thermometer code is the optimum code in terms of glitches and is simplest for allowing interdigitized layout structures. However, for larger number of bits in the encoder becomes rather large and complex. In the thesis we  presentmore work where a linear code is used. This code ends up in-between the thermometer code and the binary code in terms of erformance and complexit .