Circuit Design for All-Digital Frequency Synthesizers

Abstract: The market for low cost portable electronics is rapidly growing. Physical activity monitors, portable music players, and smart watches are fast becoming a part of daily life. As the market for wearable devices has grown, a primary concern for IC manufacturers is to provide low cost, low power and lightweight circuit solutions. In a bid to lower the costs and extend battery life there is an increased interest in using low-cost, low-power CMOS processes. As a result fully integrated systems on chips (SOC) have been realized that efficiently perform the required functions. These SOCs house digital, analog and in some cases radio circuits on a single die in a bid to reduce cost and improve productivity.Phase Locked Loops (PLLs) are a key building block for all SOCs where they are used to generate clock signals for synchronous systems. In monolithic implementations the design cost of a circuit is measured in terms of the silicon area and not the number of devices in the circuit. With the advent of all-digital techniques, there is a renewed interest in the design of compact PLLs as the area occupied by the traditional PLLs is very large due to the presence of large passive components in the loop filter and the oscillator. As a result, various digital circuit design techniques are being explored to design compact all-digital PLLs (ADPLLs) while satisfying the performance requirements for the target applications.The focus of this work is to explore new techniques for area, power and time efficient design of ADPLL component blocks. The first part of this works focuses on the feasibility of using automatic place and route (P&R) tools to synthesize a time-to-digital converter (TDC). An area efficient TDC is synthesized in a 65 nm CMOS process using automated P&R which exhibits a time resolution of 6.5 ps with an input sampling rate of 100 MS/s while occupying an area of 0.002 mm2. A modified switching scheme is also presented which reduces the power consumption of the thermometer-to-binary encoder by up to 40%.The second part of this thesis proposes a power supply filter for mitigating the affect of cyclostationary noise on the voltage controlled ring oscillator. The key idea is to raise the impedance in the current supply during the sensitive periods and lower it during insensitive periods of the oscillator operation. To demonstrate the feasibility of the proposed filter, a pseudo differential ring oscillator is designed in a 65 nm CMOS process which exhibits an rms jitter of less than 14 ps at 2.4 GHz in the presence of a 500 mV noise tone in the power supply.