Selected Applications of Switched Capacitor Circuits : RF N-Path Filters and ΣΔ Modulators

Abstract: Electronic circuits based on switches and capacitors have been used in various applications for several decades. The common switched capacitor (SC) circuits have made their career primarily in analog filters and data converters due to high immunity to capacitance mismatch in integrated circuit (IC) technologies. Recently, also in other fields, circuits using switches and capacitors appeared very attractive. In particular, tunable sampling receiver frontends and N-path RF filters have proven very useful; the latter as a tunable integrated replacement for surface acoustic wave (SAW) and bulk acoustic wave (BAW) filters. In this work addressed are applications of SC technique in ΣΔ modulators and RF bandpass filters.In a typical receiver frontend the SAW or BAW filters are placed after the antenna to suppress the out-of-band interferers (OBI) that can have power levels as high as 0 dBm. These filters by their nature are neither tunable over frequency nor programmable for different bandwidths. Recently, several SAW-less receivers have been proposed based on the idea of N-path filters that are built with switches and capacitors and driven by N-phase non-overlapping clock. N-path filters make use of baseband impedance upconversion and are tunable with clock frequency. However, with capacitors at baseband, the resulting second order RF filter can only provide a limited blocker rejection.The first contribution of this work is a tunable zero-IF receiver font-end which employs two 4-path bandpass filters in cascade that operate over the frequency range of (0.5-3) GHz. Each filter section is composed of low noise trans-conductance amplifier (LNTA) and a 4-path structure based on switches and capacitors. The second stage also serves as a downconversion mixer in this architecture. In order to avoid loading effects and thereby guarantee high blocker rejection, a voltage buffer is placed between the stages. The 4-path filter gain is estimated by linear periodically varying (LPV) model which accurately captures the RF filter gain in the presence of parasitic capacitance of the amplifier and the switches. The model is also suited to account for the possible clock phase mismatch effects. Fabricated in CMOS 65 nm technology the measured frontend has achieved out-of-band IIP3 and out-of-band P1dB of +15 dBm and +5 dBm respectively. The NF varies from 3.2 to 5.3 dB at 0.5 GHz to 3 GHz. A blocker rejection of 60 dB is achieved at 0.5 GHz which reduces gradually with frequency to 38 dB at 3 GHz.Another technique suitable for high rejection filtering at RF is based on subtraction of two bandpass filter responses with slightly different center frequencies. Combining the frequency responses in this way also results in better shaping of the filter passband. The necessary offset frequency can be obtained with one clock frequency and quadrature coupled virtual LC tanks at baseband using gm − C cells. In this work the N-path filter is adopted to serve in a low-IF receiver frontend where the effect of 1/f noise of gm cells can be mitigated. For this purpose, the offset frequencies of both filter branches are chosen to be either positive or negative against the carrier. In this setup the filter is also used as a quadrature downconversion mixer. Importantly, some image rejection is already achieved at RF and it is upto 15 dB after downconversion to IF, relaxing thereby the demands for the ultimate image rejection. Simulated in 65 nm CMOS technology the frontend achieves out-of-band IIP3 of 8 dBm, NF of less than 6 dB while image rejection (IR) at RF and IF is 4.8 dB and 15 dB, respectively.Another contribution of this work is the design of passive SC ΣΔ modulators for low frequency applications. A low frequency ultra-low-power passive modulator was designed in 65 nm CMOS technology and by exploring the design space it was optimized for signal-to-noise and distortion ratio (SNDR). Using a second order SC filter the modulator demonstrated in measurements SNDR = 67 dB and a figure of merit (FOM) of 0.296 pJ/step, which in a comparative design study was superior to its counterparts, semi-passive and active SC ΣΔ modulators.Furthermore the analysis and design procedures of passive SC ΣΔ modulator are revisited. Presented is the optimization of the noise transfer function (NTF) of second order passive SC modulator in the design space defined by the filter capacitor ratios and the feedback coefficients. Included is a detailed analysis of the thermal noise of the loop filter and the quantizer. Quantization noise, and other parasitic effects are thoroughly analyzed as well. After the optimization, high level simulations show good compliance with the measurement results. Peak SNDR of 73.7/68.4 dB, DR of 73.4/70.7 dB and MSA of -6.6/-4.3 dBFS is measured in 65 nm CMOS process for the sampling frequency of 500 kHz/250 kHz, respectively, while the attained minimum FOM is 0.17 pJ/step.