Model Based Development of Embedded Systems using Clock Constraints and Timed Automata

University dissertation from Västerås : Mälardalen University

Abstract: In modern times, the human life is intrinsically associated with real-time embedded systems (RTES) with increasingly safety-critical and mission-critical features, for instance, in domains such as automotive and avionics. These systems are characterized by stringent functional requirements and predictable timing behavior. However, the complexity of RTES has been ever increasing requiring systematic development methods. To address these concerns, modelbased frameworks and component-based design methodologies have emerged as a feasible solution. Further, system artifacts such as requirements/specifications, architectural designs as well as behavioral models like statemachine views are integrated within the development process. However, there remains several challenges to be addressed, such as, expressiveness, to represent the real-time and causality behavior, and analyzability, to support verification of functional and timing behavior during early-phases of system development. As the main research contribution, this thesis presents design and verification techniques for model-based development of RTES, addressing expressiveness and analyzability for architectural and behavioral models. To begin with, we have proposed a systematic design process to support component-based development. Next, we have provided a real-time semantic basis, in order to support expressiveness and verification for structural and behavioral models. This is achieved by defining an intuitive formal semantics for real-time component models, using ProCom, a component model developed at our research centre, and also using the CCSL (Clock Constraint specification language), an expressive language for specification of timed causality behavior. This paves the way for formal verification of both architectural and behavioral models, using model checking, as we have shown, by transforming the models into timed automata and performing verification using UPPAAL, a model checking tool based on timed automata. Finally, the research contributions are validated using representative examples of RTES as well as an industrial case-study.

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