Design of the HIBEAM/NNBAR Calorimeter and Upgrades to the ATLAS Tile Calorimeter Readout Electronics

Abstract: The Standard Model has been greatly successful in predicting the laws that govern our universe. Yet there are still seemingly missing pieces to the model. Detector development plays a crucial role in advancing our understanding of particle physics and helps answer some of the most pressing questions in the field, such as the nature of dark matter and why a matter-antimatter asymmetry is observed. This thesis has covered the work of developing detectors for two different experiments.The HIBEAM/NNBAR experimental program will be a search after neutron-sterile neutron and neutron-antineutron oscillations housed in the the European Spallation Source (ESS) in Lund, Sweden. The experiment will reach unprecedented sensitivity for free-neutron searches, surpassing the last the oscillation time limit by 3 orders of magnitude. This thesis presents an overview of the experimental goals and the opportunities afforded by the ESS infrastructure. The primary work for this thesis has been the design, simulation and construction of a prototype calorimeter for NNBAR stage of the experiment, which is presented here.The ATLAS experiment is currently undergoing upgrades to meet the requirements of the high-luminosity, high-radiation environment at the HL-LHC. This thesis provides an overview of the LHC and the ATLAS experiment, with special focus on the hadronic Tile calorimeter. TileCal will be upgraded to provide full granularity data at the lowest trigger level of the upgraded ATLAS trigger and data acquisition system. The work presented here focuses on TileCal upgrades to Daughterboard (DB), the interlink board responsible for the management of on- and off-detector data transmission. This work has been primarily focused on the design and fabrication of two printed circuit boards to test the implementation of a commercial, radiation-hardened FPGA in the upgraded DB design. The FPGA will control access to remote control JTAG in the DB Xilinx FPGA interface.