Low-Power Nanowire Circuits and Transistors

Abstract: This thesis explores several novel material systems and innovative device concepts enabled by nanowire technology. State-of-the-art fabrication techniques such as electron beam lithography and atomic layer deposition are utilized to achieve high control and quality in the device fabrication. The devices in this thesis are based on two main types of design geometries, lateral and vertical, each of which have strengths and weaknesses. The first part of the thesis describes the goals of future metal-oxide-semiconductor field-effect transistors (MOSFETs) and discusses the ultimate scalability surrounding experimental results for 15-nm-diameter InAs nanowires and how they compare to other state-of-the-art transistors. The extracted on-resistance (Ron = 250 Ω·µm) and drive currents (Ion = 1250 µA/µm) are comparable to state-of-the-art high-electron-mobility transistors (HEMTs) from MIT and quantum-well field-effect transistors from Intel. The outstanding performance is mainly attributed to the reduced access resistance achieved through an n+-i-n+ doping profile. The extracted mobilities also agree well with state-of-the-art and theoretical predictions for extremely scaled devices. The second part of the thesis discusses how nanowires may be employed to enable III-V complementary metal-oxide-semiconductor (CMOS) digital logic. Nanowires enable the formation of both n-type semiconductors and p-type semiconductors, which are a requirement for CMOS, in a single nanowire and allow for integration on a Si platform. III-V MOSFETs are frequently employed for analog applications, but there is a disconnect regarding p-type devices, which are also required for digital logic. The individual segments of the nanowire are evaluated as well as the entire nanowire in an inverter configuration. This thesis then presents a strategy for matching the drive currents n- and p-type MOSFETs. The final part of the thesis deals with a family of devices that operate according to principles fundamentally different from those of a traditional MOSFET, namely tunnel FETs (TFETs). There is a demand for steep-slope devices such as TFETs to enable supply-voltage scaling to reduce the power dissipation. Although devices have demonstrated <60 mV/decade operation, they commonly suffer from low on-currents. To maximize the drive current, the broken band gap alignment of GaSb/InAs is exploited to allow for a direct tunneling mechanism. The material system is first explored as Esaki diodes and in various doping profiles to understand the influence of doping on device performance. The devices are further evolved into TFETs by the addition of a high-k gate dielectric and an additional terminal. Experimental results display high on-currents of Ion = 310 µA/µm comparable to other state-of-the-art TFETs. Finally, an innovative design concept combining axial and radial heterostructures is utilized to design a radial TFET with a small footprint. A radial GaSb/InAs core/shell TFET provides an attractive way to increase the drive current of a TFET without compromising either device electrostatics or chip area. The functionality of radial Esaki diodes and TFETs is demonstrated and evaluated by the maximum peak currents, which are much improved as compared to their axial counterparts when normalized to the largest cross-sectional area of the nanowire, assuming a vertical device geometry, illustrating the advantage of a core--shell architecture. The dimensions of the InAs shells are below 15-nm and display clear quantization effects revealed in low-temperature electrical characterization.