Time and space efficient algorithms for packet classification and forwarding

Abstract: The Internet consists of a mesh of routers (nodes) connected by links (edges) and the traffic through the Internet is divided into flows where each flow is an ordered sequence of packets, or datagrams. Each packet consists of a header and a piece of data, also referred to as payload. The header contains information about source and destination of the packet as well as some additional information. The primary function of an Internet router is to inspect the destination address of a packet, determine in which direction, i.e. on which link, to forward the packet on its next step towards its destination and then to forward the packet. This is called forwarding and is one of the problems considered in this thesis. Forwarding is essentially a data structuring problem where a local view of the Internet surrounding the router is represented in the form of a forwarding table, where the destination address can be looked up to determine the forwarding direction. In this thesis we develop a number of forwarding table data structures with different characteristics, both for supporting the current Internet Protocol IP version 4, which uses 32-bit addressing, as well as tomorrows IP version 6 featuring 128-bit addresses. The secondary function is the ability to determine whether to forward a packet or not based on the information from one or more header fields. While the entries stored in a forwarding table are 1-dimensional intervals, the entries used for packet classification are D-dimensional, where D is typically larger than or equal to 5. As a result, packet classification requires some degree of brute force, either in terms of parallel processing or huge amount of memory to achieve guaranteed performance. We have developed efficient algorithms for reducing the number of bits involved in the actual D-dimensional classification. These algorithms can be used to improve performance of both brute force hardware classifiers and heuristic software based classifiers. We first work on a purely theoretical problem called implicit selection where the solution as such does not have any impact whatsoever on forwarding and packet classification. However, in the process of solving the implicit selection problem, we have worked with numerous in-place techniques that becomes extremely useful when dealing with some aspects of packet classification and forwarding later on. It is interesting to see how techniques for achieving good performance in Asymptopia can be used also in the real world. The next step is to develop a data structure called hybrid tree where the keys are stored with minimal storage overhead and the lookup cost is independent of the number of keys in a non-trivial way. We also show how to engineer both static 128-bit single field classification without storage overhead as well as dynamic 128-bit classification with roughly 40% storage overhead that support reasonably fast update operations. Next we deal with compression state lookup for IPv6 header compression, using a dynamic move-to-root Patricia tree which adapts to the traffic pattern in an on-line fashion, followed by classification of fragmented packets, using a highly dynamic dictionary data structure featuring automated garbage collection. This is followed by two forwarding algorithms with completely different properties. The first algorithm is called XTC and supports fast lookups and good average compression but not incremental updates whereas the second algorithm is based on hybrid trees and features fast lookups and updates as well as good table compression. Finally, we present a packet classification algorithm which reduces both silicon area and power consumption for a hardware implementation. Our approach is to use hybrid trees to compress the addresses to reduce the total number of bits involved in final parallel processing. For IPv6 multifield classification, we can reduce the total number of transistors by 50% and the power consumption by over 80% compared to existing technologies for interval matching in hardware.