Test Cost Reduction of 3D Stacked ICs : Test Planning and Test Flow Selection

Abstract: Ever higher levels of integration within the Integrated Circuit (IC) tomeet progressively widening scope of its application in respect of functionality,size, performance and manufacturing issues inspired developmentof the three-dimensional (3D) Stacked IC as a device havingviable architecture. However, with increased complexity, manufacturingcost increased. The manufacturing cost includes the test cost component,essential to ensure fidelity to the desired design specifications.Of the several challenges faced by 3D Stacked ICs, cost efficient testingof the manufactured product is most critical. Reduction of test cost for3D Stacked ICs through test planning along with test flow selectionmethods is addressed in this thesis.Test planning for 3D Stacked ICs is performed by reducing the totalcost accounting for the test time and Design-for-Test (DfT) hardware.Three test architecture standards are used: Built-In Self-Test (BIST),IEEE 1149.1 and IEEE 1500. The test cost corresponding to each testarchitecture is detailed and test planning algorithms are proposed. Thealgorithms are implemented and experiments are performed on several3D Stacked IC designs formed with multiple 2D IC benchmarks. Forexperiment, a test flow is presented that comprises the wafer test ofeach chip followed by test of the entire packaged IC. Results indicateeffectiveness of the proposed algorithms in terms of test cost.Test flow selection, to decide stages at which tests are to be performed,for 3D Stacked ICs is addressed motivated towards the reductionof test time required to produce each single fault-free package. Amodel to calculate the total test time for any given test flow is detailed.An algorithm is proposed to find a test flow for reducing test time.The algorithm is implemented and executed on several 3D Stacked ICdesigns with up to ten chips in the stack. Results indicate considerablereductions in test time as compared to predetermined test flows.