An approach to extraction of pipeline structures for VLSI high-level synthesis

Abstract: One of the concerns in high-level synthesis is how to efficiently exploit the potential concurrency in a design. Pipelining achieves a high degree of concurrency, and a certain structural regularity through exploitation of locality in communication. However, pipelining cannot be applied to all designs. Pipeline extraction localizes parts of the design that can benefit form pipelining. Such extraction is a first step in pipeline synthesis. While current pipeline synthesis systems are restricted to exploitation of loops, this thesis addresses the problem of extracting pipeline structures from arbitrary designs without apparent pipelining properties. Therefore, an approach that is based on pipelining of individual computations is explored. Still, loops constitute an important special case, and can be encompassed within the approach in an efficient way. The general formulation of the approach cannot be applied directly for extraction purposes, because of a combinatorial explosion of the design space. An iterative search strategy to handle this problem i presented. A specific polynomial-time algorithm based on this strategy, using several additional heuristics to reduce complexity, has been implemented in the PiX system, which operates as a preprocessor to the CAMAD VLSI design system. The input to PiX is an algorithmic description in a Pascal-like language, which is translated into the Extended Timed Petri Net (ETPN) representation. The extraction is realized as analysis of and transformations on the ETPN. Preliminary results from PiX show that the approach is feasible and useful for realistic designs.